diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2015-09-01 11:23:09 +0200 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:50:35 +0900 |
| commit | b0a95d71ac21cdef685abd0691891f318fd08435 (patch) | |
| tree | 3059719de20f2e811d6ef44b528bc1fb458f4dd0 | |
| parent | 77d83016100c1433255e6351b54d0ba7cf241dea (diff) | |
ARM: DTS: exynos5420: add GSCL block parent clock management to pm domain
Add support for restoring GSCALLER parent clocks configuration when GSCL
power domain is turned on.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
| -rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 1711c9b82a28..907923e233bb 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -299,8 +299,10 @@ compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; - clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>, <&clock CLK_FIMC_3AA>; - clock-names = "asb0", "asb1", "asb2"; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK300_GSCL>, + <&clock CLK_MOUT_USER_ACLK300_GSCL>, <&clock CLK_GSCL0>, + <&clock CLK_GSCL1>, <&clock CLK_FIMC_3AA>; + clock-names = "oscclk", "pclk0", "clk0", "asb0", "asb1", "asb2"; }; isp_pd: power-domain@10044020 { |