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authorChris Wilson <chris@chris-wilson.co.uk>2020-11-11 14:51:55 +0000
committerJani Nikula <jani.nikula@intel.com>2022-05-02 14:27:24 +0300
commitfa91abc6386b38bb88bf97045bef8aa9b4fb5572 (patch)
treeb7f4c1aa72ae00c57f4d8cfd65358dd8404f4abe
parentc21406fe57a267cfcb272c01f34c4efcef6c3cf9 (diff)
HAX x86/rapl: Treat Tigerlake like Icelake
Since Tigerlake seems to have inherited its cstates and other rapl power caps from Icelake, assume it also follows Icelake for its rapl events. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-rw-r--r--arch/x86/events/rapl.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 77e3a47af5ad..38533df331bb 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -807,6 +807,8 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &model_skl),
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &model_skl),
X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr),
+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &model_skl),
+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &model_skl),
{},
};
MODULE_DEVICE_TABLE(x86cpu, rapl_model_match);