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authorSuneel Garapati <suneel.garapati@xilinx.com>2015-08-19 15:23:21 +0530
committerAlexandre Belloni <alexandre.belloni@free-electrons.com>2015-09-05 19:37:19 +0200
commit12ece40d9196e01961192fc25cfdaf22392520de (patch)
treec633c70054db2affb3b723f0840d426ef23d29f9 /Documentation
parenta038c3aa9f3afe9ab97a75827789859fb4af5767 (diff)
devicetree: bindings: rtc: add bindings for xilinx zynqmp rtc
adds file for description on device node bindings for RTC found on Xilinx Zynq Ultrascale+ MPSoC. Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/rtc/xlnx-rtc.txt25
1 files changed, 25 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt b/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
new file mode 100644
index 000000000000..0df6f016b1b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
@@ -0,0 +1,25 @@
+* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
+
+RTC controller for the Xilinx Zynq MPSoC Real Time Clock
+Separate IRQ lines for seconds and alarm
+
+Required properties:
+- compatible: Should be "xlnx,zynqmp-rtc"
+- reg: Physical base address of the controller and length
+ of memory mapped region.
+- interrupts: IRQ lines for the RTC.
+- interrupt-names: interrupt line names eg. "sec" "alarm"
+
+Optional:
+- calibration: calibration value for 1 sec period which will
+ be programmed directly to calibration register
+
+Example:
+rtc: rtc@ffa60000 {
+ compatible = "xlnx,zynqmp-rtc";
+ reg = <0x0 0xffa60000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 26 4>, <0 27 4>;
+ interrupt-names = "alarm", "sec";
+ calibration = <0x198233>;
+};