diff options
| author | Paul Walmsley <paul@pwsan.com> | 2011-02-25 15:49:53 -0700 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2011-03-07 20:02:05 -0700 |
| commit | 0fd0c21be71293d8a54d9075b18b5a25a1868057 (patch) | |
| tree | ebf500cb2d7b0c104fc1e1c190aa3b2457d987c8 /arch/arm/mach-omap2/pm24xx.c | |
| parent | c6461f5c5970833cf28c5096cdfc7a095eb3bbb5 (diff) | |
OMAP2: clock: add DPLL autoidle support
Add the necessary code and data to allow the clock framework to enable
and disable the OMAP2 DPLL autoidle state. This is so the direct
register access can be moved out of the mach-omap2/pm24xx.c code, and other
code that needs to control this (e.g., CPUIdle) can do so via an API.
As part of this patch, remove the pm24xx.c code that formerly wrote
directly to the autoidle bits.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/pm24xx.c')
| -rw-r--r-- | arch/arm/mach-omap2/pm24xx.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index e983c8301f55..297bb21061b8 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -378,6 +378,7 @@ static void __init prcm_setup_regs(void) { int i, num_mem_banks; struct powerdomain *pwrdm; + u32 v; /* Enable autoidle */ omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, @@ -468,11 +469,12 @@ static void __init prcm_setup_regs(void) omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, CM_AUTOIDLE); - /* Put DPLL and both APLLs into autoidle mode */ - omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | - (0x03 << OMAP24XX_AUTO_96M_SHIFT) | - (0x03 << OMAP24XX_AUTO_54M_SHIFT), - PLL_MOD, CM_AUTOIDLE); + /* Put both APLLs into autoidle mode */ + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); + v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT); + v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) | + (0x03 << OMAP24XX_AUTO_54M_SHIFT); + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | OMAP24XX_AUTO_WDT1_MASK | |