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authorThomas Abraham <thomas.ab@samsung.com>2009-09-08 14:26:00 +0900
committerBen Dooks <ben-linux@fluff.org>2009-09-16 00:50:05 +0100
commit9adb15b80bf1dc6b30a584e76efc876dfd029a13 (patch)
treef1ac3dd776031e57b4d12f398cb4631e5dd84de3 /arch/arm/plat-s3c64xx
parentbaa28e3530375e0bef2c53243634a1c78f5c02f3 (diff)
ARM: S3C6410: use correct divider_shift in setrate_clksrc()
In s3c64xx_setrate_clksrc() we used sclk->shift, but actually need to use sclk->divider_shift to correctly calculate the value for the divider register. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [ben-linux@fluff.org: Minor re-indentation of description] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx')
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index febac1950d8e..c972d2f8c271 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -302,8 +302,8 @@ static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
return -EINVAL;
val = __raw_readl(reg);
- val &= ~(0xf << sclk->shift);
- val |= (div - 1) << sclk->shift;
+ val &= ~(0xf << sclk->divider_shift);
+ val |= (div - 1) << sclk->divider_shift;
__raw_writel(val, reg);
return 0;