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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2021-09-01 18:31:45 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2021-09-01 18:31:45 -0700 |
| commit | 6104dde096eba9f443845686a2c4b3fa31129eb4 (patch) | |
| tree | f8677df0adcc573f5acf135adfddfaa2c7bc7674 /arch/m68k/include/asm/m5441xsim.h | |
| parent | c07f191907e7d7e04034a2b9657a6bbf1355c60a (diff) | |
| parent | db87db65c1059f3be04506d122f8ec9b2fa3b05e (diff) | |
Merge tag 'm68knommu-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu updates from Greg Ungerer:
"A collection of fixes:
- flexcan platform support (for m5441x)
- fix CONFIG_ROMKERNEL linking
- fix compilation when CONFIG_ISA_DMA_API is set
- fix local ColdFire clk_enable() for NULL clk"
* tag 'm68knommu-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
m68knommu: only set CONFIG_ISA_DMA_API for ColdFire sub-arch
m68k: coldfire: return success for clk_enable(NULL)
m68k: m5441x: add flexcan support
m68k: stmark2: update board setup
m68k/nommu: prevent setting ROMKERNEL when ROM is not set
Diffstat (limited to 'arch/m68k/include/asm/m5441xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5441xsim.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h index e091e36d3464..f48cf63bd782 100644 --- a/arch/m68k/include/asm/m5441xsim.h +++ b/arch/m68k/include/asm/m5441xsim.h @@ -73,6 +73,12 @@ #define MCFINT0_FECENTC1 55 /* on interrupt controller 1 */ +#define MCFINT1_FLEXCAN0_IFL 0 +#define MCFINT1_FLEXCAN0_BOFF 1 +#define MCFINT1_FLEXCAN0_ERR 3 +#define MCFINT1_FLEXCAN1_IFL 4 +#define MCFINT1_FLEXCAN1_BOFF 5 +#define MCFINT1_FLEXCAN1_ERR 7 #define MCFINT1_UART4 48 #define MCFINT1_UART5 49 #define MCFINT1_UART6 50 @@ -314,4 +320,17 @@ #define MCF_IRQ_SDHC (MCFINT2_VECBASE + MCFINT2_SDHC) #define MCFSDHC_CLK (MCFSDHC_BASE + 0x2c) +/* + * Flexcan module + */ +#define MCFFLEXCAN_BASE0 0xfc020000 +#define MCFFLEXCAN_BASE1 0xfc024000 +#define MCFFLEXCAN_SIZE 0x4000 +#define MCF_IRQ_IFL0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_IFL) +#define MCF_IRQ_BOFF0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_BOFF) +#define MCF_IRQ_ERR0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_ERR) +#define MCF_IRQ_IFL1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_IFL) +#define MCF_IRQ_BOFF1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_BOFF) +#define MCF_IRQ_ERR1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_ERR) + #endif /* m5441xsim_h */ |