Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "The whole series has been sitting in -next for quite a while with no
  complaints.  The last change to the series was before the weekend the
  removal of an SPI patch which Grant - even though previously acked by
  himself - appeared to raise objections.  So I removed it until the
  situation is clarified.  Other than that all the patches have the acks
  from their respective maintainers, all MIPS and x86 defconfigs are
  building fine and I'm not aware of any problems introduced by this
  series.

  Among the key features for this patch series is a sizable patchset for
  Lantiq which among other things introduces support for Lantiq's
  flagship product, the FALCON SOC.  It also means that the opensource
  developers behind this patchset have overtaken Lantiq's competing
  inhouse development team that was working behind closed doors.

  Less noteworthy the ath79 patchset which adds support for a few more
  chip variants, cleanups and fixes.  Finally the usual dose of tweaking
  of generic code."

Fix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where
printk spelling fixes clashed with file move and eventual removal of the
printk.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits)
  MIPS: lantiq: remove orphaned code
  MIPS: Remove all -Wall and almost all -Werror usage from arch/mips.
  MIPS: lantiq: implement support for FALCON soc
  MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc
  MTD: MIPS: lantiq: implement OF support
  watchdog: MIPS: lantiq: implement OF support and minor fixes
  SERIAL: MIPS: lantiq: implement OF support
  GPIO: MIPS: lantiq: convert gpio-stp-xway to OF
  GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio
  GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder
  MIPS: pci: convert lantiq driver to OF
  MIPS: lantiq: convert dma to platform driver
  MIPS: lantiq: implement support for clkdev api
  MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()
  OF: MIPS: lantiq: implement irq_domain support
  OF: MIPS: lantiq: implement OF support
  MIPS: lantiq: drop mips_machine support
  OF: PCI: const usage needed by MIPS
  MIPS: Cavium: Remove smp_reserve_lock.
  MIPS: Move cache setup to setup_arch().
  ...

1 files changed, 115 insertions, 0 deletions

diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
new file mode 100644
index 000000000000..248429ab2622
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom.c
@@ -0,0 +1,115 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/export.h>
+#include <linux/clk.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+
+#include <lantiq_soc.h>
+
+#include "../prom.h"
+
+#define SOC_DANUBE	"Danube"
+#define SOC_TWINPASS	"Twinpass"
+#define SOC_AMAZON_SE	"Amazon_SE"
+#define SOC_AR9		"AR9"
+#define SOC_GR9		"GR9"
+#define SOC_VR9		"VR9"
+
+#define COMP_DANUBE	"lantiq,danube"
+#define COMP_TWINPASS	"lantiq,twinpass"
+#define COMP_AMAZON_SE	"lantiq,ase"
+#define COMP_AR9	"lantiq,ar9"
+#define COMP_GR9	"lantiq,gr9"
+#define COMP_VR9	"lantiq,vr9"
+
+#define PART_SHIFT	12
+#define PART_MASK	0x0FFFFFFF
+#define REV_SHIFT	28
+#define REV_MASK	0xF0000000
+
+void __init ltq_soc_detect(struct ltq_soc_info *i)
+{
+	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
+	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
+	sprintf(i->rev_type, "1.%d", i->rev);
+	switch (i->partnum) {
+	case SOC_ID_DANUBE1:
+	case SOC_ID_DANUBE2:
+		i->name = SOC_DANUBE;
+		i->type = SOC_TYPE_DANUBE;
+		i->compatible = COMP_DANUBE;
+		break;
+
+	case SOC_ID_TWINPASS:
+		i->name = SOC_TWINPASS;
+		i->type = SOC_TYPE_DANUBE;
+		i->compatible = COMP_TWINPASS;
+		break;
+
+	case SOC_ID_ARX188:
+	case SOC_ID_ARX168_1:
+	case SOC_ID_ARX168_2:
+	case SOC_ID_ARX182:
+		i->name = SOC_AR9;
+		i->type = SOC_TYPE_AR9;
+		i->compatible = COMP_AR9;
+		break;
+
+	case SOC_ID_GRX188:
+	case SOC_ID_GRX168:
+		i->name = SOC_GR9;
+		i->type = SOC_TYPE_AR9;
+		i->compatible = COMP_GR9;
+		break;
+
+	case SOC_ID_AMAZON_SE_1:
+	case SOC_ID_AMAZON_SE_2:
+#ifdef CONFIG_PCI
+		panic("ase is only supported for non pci kernels");
+#endif
+		i->name = SOC_AMAZON_SE;
+		i->type = SOC_TYPE_AMAZON_SE;
+		i->compatible = COMP_AMAZON_SE;
+		break;
+
+	case SOC_ID_VRX282:
+	case SOC_ID_VRX268:
+	case SOC_ID_VRX288:
+		i->name = SOC_VR9;
+		i->type = SOC_TYPE_VR9;
+		i->compatible = COMP_VR9;
+		break;
+
+	case SOC_ID_GRX268:
+	case SOC_ID_GRX288:
+		i->name = SOC_GR9;
+		i->type = SOC_TYPE_VR9;
+		i->compatible = COMP_GR9;
+		break;
+
+	case SOC_ID_VRX268_2:
+	case SOC_ID_VRX288_2:
+		i->name = SOC_VR9;
+		i->type = SOC_TYPE_VR9_2;
+		i->compatible = COMP_VR9;
+		break;
+
+	case SOC_ID_GRX282_2:
+	case SOC_ID_GRX288_2:
+		i->name = SOC_GR9;
+		i->type = SOC_TYPE_VR9_2;
+		i->compatible = COMP_GR9;
+		break;
+
+	default:
+		unreachable();
+		break;
+	}
+}