sh: Migrate common board headers to mach-common/.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

15 files changed, 952 insertions, 0 deletions

diff --git a/arch/sh/include/mach-common/mach/edosk7705.h b/arch/sh/include/mach-common/mach/edosk7705.h
new file mode 100644
index 000000000000..5bdc9d9be3de
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/edosk7705.h
@@ -0,0 +1,30 @@
+/*
+ * include/asm-sh/edosk7705.h
+ *
+ * Modified version of io_se.h for the EDOSK7705 specific functions.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * IO functions for an Hitachi EDOSK7705 development board
+ */
+
+#ifndef __ASM_SH_EDOSK7705_IO_H
+#define __ASM_SH_EDOSK7705_IO_H
+
+#include <asm/io_generic.h>
+
+extern unsigned char sh_edosk7705_inb(unsigned long port);
+extern unsigned int sh_edosk7705_inl(unsigned long port);
+
+extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
+extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
+
+extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
+extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
+extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
+extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
+
+extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
+
+#endif /* __ASM_SH_EDOSK7705_IO_H */
diff --git a/arch/sh/include/mach-common/mach/highlander.h b/arch/sh/include/mach-common/mach/highlander.h
new file mode 100644
index 000000000000..306f7359f7d4
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/highlander.h
@@ -0,0 +1,198 @@
+#ifndef __ASM_SH_RENESAS_R7780RP_H
+#define __ASM_SH_RENESAS_R7780RP_H
+
+/* Box specific addresses.  */
+#if defined(CONFIG_SH_R7780MP)
+#define PA_BCR          0xa4000000      /* FPGA */
+#define PA_SDPOW	(-1)
+
+#define PA_IRLMSK       (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON       (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_IRLPRI1      (PA_BCR+0x0004) /* Interrupt Priorty 1 */
+#define PA_IRLPRI2      (PA_BCR+0x0006) /* Interrupt Priorty 2 */
+#define PA_IRLPRI3      (PA_BCR+0x0008) /* Interrupt Priorty 3 */
+#define PA_IRLPRI4      (PA_BCR+0x000a) /* Interrupt Priorty 4 */
+#define PA_RSTCTL       (PA_BCR+0x000c) /* Reset Control */
+#define PA_PCIBD        (PA_BCR+0x000e) /* PCI Board detect control */
+#define PA_PCICD        (PA_BCR+0x0010) /* PCI Conector detect control */
+#define PA_EXTGIO       (PA_BCR+0x0016) /* Extension GPIO Control */
+#define PA_IVDRMON      (PA_BCR+0x0018) /* iVDR Moniter control */
+#define PA_IVDRCTL      (PA_BCR+0x001a) /* iVDR control */
+#define PA_OBLED        (PA_BCR+0x001c) /* On Board LED control */
+#define PA_OBSW         (PA_BCR+0x001e) /* On Board Switch control */
+#define PA_AUDIOSEL     (PA_BCR+0x0020) /* Sound Interface Select control */
+#define PA_EXTPLR       (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL        (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL     (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR     (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS       (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS       (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBSW         (PA_BCR+0x0200) /* Debug Board Switch control */
+#define PA_CFCTL        (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW        (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR   (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR0       (PA_BCR+0x0400) /* SCIF0 Serial mode control */
+#define PA_SCBRR0       (PA_BCR+0x0404) /* SCIF0 Bit rate control */
+#define PA_SCSCR0       (PA_BCR+0x0408) /* SCIF0 Serial control */
+#define PA_SCFTDR0      (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
+#define PA_SCFSR0       (PA_BCR+0x0410) /* SCIF0 Serial status control */
+#define PA_SCFRDR0      (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
+#define PA_SCFCR0       (PA_BCR+0x0418) /* SCIF0 FIFO control */
+#define PA_SCTFDR0      (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
+#define PA_SCRFDR0      (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
+#define PA_SCSPTR0      (PA_BCR+0x0424) /* SCIF0 Serial Port control */
+#define PA_SCLSR0       (PA_BCR+0x0428) /* SCIF0 Line Status control */
+#define PA_SCRER0       (PA_BCR+0x042c) /* SCIF0 Serial Error control */
+#define PA_SCSMR1       (PA_BCR+0x0500) /* SCIF1 Serial mode control */
+#define PA_SCBRR1       (PA_BCR+0x0504) /* SCIF1 Bit rate control */
+#define PA_SCSCR1       (PA_BCR+0x0508) /* SCIF1 Serial control */
+#define PA_SCFTDR1      (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
+#define PA_SCFSR1       (PA_BCR+0x0510) /* SCIF1 Serial status control */
+#define PA_SCFRDR1      (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
+#define PA_SCFCR1       (PA_BCR+0x0518) /* SCIF1 FIFO control */
+#define PA_SCTFDR1      (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
+#define PA_SCRFDR1      (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
+#define PA_SCSPTR1      (PA_BCR+0x0524) /* SCIF1 Serial Port control */
+#define PA_SCLSR1       (PA_BCR+0x0528) /* SCIF1 Line Status control */
+#define PA_SCRER1       (PA_BCR+0x052c) /* SCIF1 Serial Error control */
+#define PA_SMCR         (PA_BCR+0x0600) /* 2-wire Serial control */
+#define PA_SMSMADR      (PA_BCR+0x0602) /* 2-wire Serial Slave control */
+#define PA_SMMR         (PA_BCR+0x0604) /* 2-wire Serial Mode control */
+#define PA_SMSADR1      (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
+#define PA_SMTRDR1      (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
+#define PA_VERREG       (PA_BCR+0x0700) /* FPGA Version Register */
+#define PA_POFF         (PA_BCR+0x0800) /* System Power Off control */
+#define PA_PMR          (PA_BCR+0x0900) /*  */
+
+#define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
+#define IVDR_CK_ON	8		/* iVDR Clock ON */
+
+#elif defined(CONFIG_SH_R7780RP)
+#define PA_POFF		(-1)
+
+#define PA_BCR		0xa5000000	/* FPGA */
+#define	PA_IRLMSK	(PA_BCR+0x0000)	/* Interrupt Mask control */
+#define PA_IRLMON	(PA_BCR+0x0002)	/* Interrupt Status control */
+#define	PA_SDPOW	(PA_BCR+0x0004)	/* SD Power control */
+#define	PA_RSTCTL	(PA_BCR+0x0006)	/* Device Reset control */
+#define	PA_PCIBD	(PA_BCR+0x0008)	/* PCI Board detect control */
+#define	PA_PCICD	(PA_BCR+0x000a)	/* PCI Conector detect control */
+#define	PA_ZIGIO1	(PA_BCR+0x000c)	/* Zigbee IO control 1 */
+#define	PA_ZIGIO2	(PA_BCR+0x000e)	/* Zigbee IO control 2 */
+#define	PA_ZIGIO3	(PA_BCR+0x0010)	/* Zigbee IO control 3 */
+#define	PA_ZIGIO4	(PA_BCR+0x0012)	/* Zigbee IO control 4 */
+#define	PA_IVDRMON	(PA_BCR+0x0014)	/* iVDR Moniter control */
+#define	PA_IVDRCTL	(PA_BCR+0x0016)	/* iVDR control */
+#define PA_OBLED	(PA_BCR+0x0018)	/* On Board LED control */
+#define PA_OBSW		(PA_BCR+0x001a)	/* On Board Switch control */
+#define PA_AUDIOSEL	(PA_BCR+0x001c)	/* Sound Interface Select control */
+#define PA_EXTPLR	(PA_BCR+0x001e)	/* Extention Pin Polarity control */
+#define PA_TPCTL	(PA_BCR+0x0100)	/* Touch Panel Access control */
+#define PA_TPDCKCTL	(PA_BCR+0x0102)	/* Touch Panel Access data control */
+#define PA_TPCTLCLR	(PA_BCR+0x0104)	/* Touch Panel Access control */
+#define PA_TPXPOS	(PA_BCR+0x0106)	/* Touch Panel X position control */
+#define PA_TPYPOS	(PA_BCR+0x0108)	/* Touch Panel Y position control */
+#define PA_DBDET	(PA_BCR+0x0200)	/* Debug Board detect control */
+#define PA_DBDISPCTL	(PA_BCR+0x0202)	/* Debug Board Dot timing control */
+#define PA_DBSW		(PA_BCR+0x0204)	/* Debug Board Switch control */
+#define PA_CFCTL	(PA_BCR+0x0300)	/* CF Timing control */
+#define PA_CFPOW	(PA_BCR+0x0302)	/* CF Power control */
+#define PA_CFCDINTCLR	(PA_BCR+0x0304)	/* CF Insert Interrupt clear */
+#define PA_SCSMR	(PA_BCR+0x0400)	/* SCIF Serial mode control */
+#define PA_SCBRR	(PA_BCR+0x0402)	/* SCIF Bit rate control */
+#define PA_SCSCR	(PA_BCR+0x0404)	/* SCIF Serial control */
+#define PA_SCFDTR	(PA_BCR+0x0406)	/* SCIF Send FIFO control */
+#define PA_SCFSR	(PA_BCR+0x0408)	/* SCIF Serial status control */
+#define PA_SCFRDR	(PA_BCR+0x040a)	/* SCIF Receive FIFO control */
+#define PA_SCFCR	(PA_BCR+0x040c)	/* SCIF FIFO control */
+#define PA_SCFDR	(PA_BCR+0x040e)	/* SCIF FIFO data control */
+#define PA_SCLSR	(PA_BCR+0x0412)	/* SCIF Line Status control */
+#define PA_SMCR		(PA_BCR+0x0500)	/* 2-wire Serial control */
+#define PA_SMSMADR	(PA_BCR+0x0502)	/* 2-wire Serial Slave control */
+#define PA_SMMR		(PA_BCR+0x0504)	/* 2-wire Serial Mode control */
+#define PA_SMSADR1	(PA_BCR+0x0506)	/* 2-wire Serial Address1 control */
+#define PA_SMTRDR1	(PA_BCR+0x0546)	/* 2-wire Serial Data1 control */
+#define PA_VERREG	(PA_BCR+0x0600)	/* FPGA Version Register */
+
+#define PA_AX88796L	0xa5800400	/* AX88796L Area */
+#define PA_SC1602BSLB	0xa6000000	/* SC1602BSLB Area */
+#define PA_IDE_OFFSET	0x1f0		/* CF IDE Offset */
+#define AX88796L_IO_BASE	0x1000	/* AX88796L IO Base Address */
+
+#define IRLCNTR1	(PA_BCR + 0)	/* Interrupt Control Register1 */
+
+#define IVDR_CK_ON	8		/* iVDR Clock ON */
+
+#elif defined(CONFIG_SH_R7785RP)
+#define PA_BCR		0xa4000000	/* FPGA */
+#define PA_SDPOW	(-1)
+
+#define	PA_PCISCR	(PA_BCR+0x0000)
+#define PA_IRLPRA	(PA_BCR+0x0002)
+#define	PA_IRLPRB	(PA_BCR+0x0004)
+#define	PA_IRLPRC	(PA_BCR+0x0006)
+#define	PA_IRLPRD	(PA_BCR+0x0008)
+#define IRLCNTR1	(PA_BCR+0x0010)
+#define	PA_IRLPRE	(PA_BCR+0x000a)
+#define	PA_IRLPRF	(PA_BCR+0x000c)
+#define	PA_EXIRLCR	(PA_BCR+0x000e)
+#define	PA_IRLMCR1	(PA_BCR+0x0010)
+#define	PA_IRLMCR2	(PA_BCR+0x0012)
+#define	PA_IRLSSR1	(PA_BCR+0x0014)
+#define	PA_IRLSSR2	(PA_BCR+0x0016)
+#define PA_CFTCR	(PA_BCR+0x0100)
+#define PA_CFPCR	(PA_BCR+0x0102)
+#define PA_PCICR	(PA_BCR+0x0110)
+#define PA_IVDRCTL	(PA_BCR+0x0112)
+#define PA_IVDRSR	(PA_BCR+0x0114)
+#define PA_PDRSTCR	(PA_BCR+0x0116)
+#define PA_POFF		(PA_BCR+0x0120)
+#define PA_LCDCR	(PA_BCR+0x0130)
+#define PA_TPCR		(PA_BCR+0x0140)
+#define PA_TPCKCR	(PA_BCR+0x0142)
+#define PA_TPRSTR	(PA_BCR+0x0144)
+#define PA_TPXPDR	(PA_BCR+0x0146)
+#define PA_TPYPDR	(PA_BCR+0x0148)
+#define PA_GPIOPFR	(PA_BCR+0x0150)
+#define PA_GPIODR	(PA_BCR+0x0152)
+#define PA_OBLED	(PA_BCR+0x0154)
+#define PA_SWSR		(PA_BCR+0x0156)
+#define PA_VERREG	(PA_BCR+0x0158)
+#define PA_SMCR		(PA_BCR+0x0200)
+#define PA_SMSMADR	(PA_BCR+0x0202)
+#define PA_SMMR		(PA_BCR+0x0204)
+#define PA_SMSADR1	(PA_BCR+0x0206)
+#define PA_SMSADR32	(PA_BCR+0x0244)
+#define PA_SMTRDR1	(PA_BCR+0x0246)
+#define PA_SMTRDR16	(PA_BCR+0x0264)
+#define PA_CU3MDR	(PA_BCR+0x0300)
+#define PA_CU5MDR	(PA_BCR+0x0302)
+#define PA_MMSR		(PA_BCR+0x0400)
+
+#define IVDR_CK_ON	4		/* iVDR Clock ON */
+#endif
+
+#define HL_FPGA_IRQ_BASE	200
+#define HL_NR_IRL		15
+
+#define IRQ_AX88796		(HL_FPGA_IRQ_BASE + 0)
+#define IRQ_CF			(HL_FPGA_IRQ_BASE + 1)
+#define IRQ_PSW			(HL_FPGA_IRQ_BASE + 2)
+#define IRQ_EXT0		(HL_FPGA_IRQ_BASE + 3)
+#define IRQ_EXT1		(HL_FPGA_IRQ_BASE + 4)
+#define IRQ_EXT2		(HL_FPGA_IRQ_BASE + 5)
+#define IRQ_EXT3		(HL_FPGA_IRQ_BASE + 6)
+#define IRQ_EXT4		(HL_FPGA_IRQ_BASE + 7)
+#define IRQ_EXT5		(HL_FPGA_IRQ_BASE + 8)
+#define IRQ_EXT6		(HL_FPGA_IRQ_BASE + 9)
+#define IRQ_EXT7		(HL_FPGA_IRQ_BASE + 10)
+#define IRQ_SMBUS		(HL_FPGA_IRQ_BASE + 11)
+#define IRQ_TP			(HL_FPGA_IRQ_BASE + 12)
+#define IRQ_RTC			(HL_FPGA_IRQ_BASE + 13)
+#define IRQ_TH_ALERT		(HL_FPGA_IRQ_BASE + 14)
+#define IRQ_SCIF0		(HL_FPGA_IRQ_BASE + 15)
+#define IRQ_SCIF1		(HL_FPGA_IRQ_BASE + 16)
+
+unsigned char *highlander_plat_irq_setup(void);
+
+#endif  /* __ASM_SH_RENESAS_R7780RP */
diff --git a/arch/sh/include/mach-common/mach/hp6xx.h b/arch/sh/include/mach-common/mach/hp6xx.h
new file mode 100644
index 000000000000..0d4165a32dcd
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/hp6xx.h
@@ -0,0 +1,58 @@
+#ifndef __ASM_SH_HP6XX_H
+#define __ASM_SH_HP6XX_H
+
+/*
+ * Copyright (C) 2003, 2004, 2005  Andriy Skulysh
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define HP680_BTN_IRQ		32	/* IRQ0_IRQ */
+#define HP680_TS_IRQ		35	/* IRQ3_IRQ */
+#define HP680_HD64461_IRQ	36	/* IRQ4_IRQ */
+
+#define DAC_LCD_BRIGHTNESS	0
+#define DAC_SPEAKER_VOLUME	1
+
+#define PGDR_OPENED		0x01
+#define PGDR_MAIN_BATTERY_OUT	0x04
+#define PGDR_PLAY_BUTTON	0x08
+#define PGDR_REWIND_BUTTON	0x10
+#define PGDR_RECORD_BUTTON	0x20
+
+#define PHDR_TS_PEN_DOWN	0x08
+
+#define PJDR_LED_BLINK		0x02
+
+#define PKDR_LED_GREEN		0x10
+
+#define SCPDR_TS_SCAN_ENABLE	0x20
+#define SCPDR_TS_SCAN_Y		0x02
+#define SCPDR_TS_SCAN_X		0x01
+
+#define SCPCR_TS_ENABLE		0x405
+#define SCPCR_TS_MASK		0xc0f
+
+#define ADC_CHANNEL_TS_Y	1
+#define ADC_CHANNEL_TS_X	2
+#define ADC_CHANNEL_BATTERY	3
+#define ADC_CHANNEL_BACKUP	4
+#define ADC_CHANNEL_CHARGE	5
+
+#define HD64461_GPADR_SPEAKER	0x01
+#define HD64461_GPADR_PCMCIA0	(0x02|0x08)
+
+#define HD64461_GPBDR_LCDOFF	0x01
+#define HD64461_GPBDR_LCD_CONTRAST_MASK	0x78
+#define HD64461_GPBDR_LED_RED	0x80
+
+#include <asm/hd64461.h>
+#include <asm/io.h>
+
+#define PJDR	0xa4000130
+#define PKDR	0xa4000132
+
+#endif /* __ASM_SH_HP6XX_H */
diff --git a/arch/sh/include/mach-common/mach/lboxre2.h b/arch/sh/include/mach-common/mach/lboxre2.h
new file mode 100644
index 000000000000..e6d160504923
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/lboxre2.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SH_LBOXRE2_H
+#define __ASM_SH_LBOXRE2_H
+
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * NTT COMWARE L-BOX RE2 support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define IRQ_CF1		9	/* CF1 */
+#define IRQ_CF0		10	/* CF0 */
+#define IRQ_INTD	11	/* INTD */
+#define IRQ_ETH1	12	/* Ether1 */
+#define IRQ_ETH0	13	/* Ether0 */
+#define IRQ_INTA	14	/* INTA */
+
+void init_lboxre2_IRQ(void);
+
+#define __IO_PREFIX	lboxre2
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_LBOXRE2_H */
diff --git a/arch/sh/include/mach-common/mach/magicpanelr2.h b/arch/sh/include/mach-common/mach/magicpanelr2.h
new file mode 100644
index 000000000000..c644a77ee357
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/magicpanelr2.h
@@ -0,0 +1,67 @@
+/*
+ *  include/asm-sh/magicpanelr2.h
+ *
+ *  Copyright (C) 2007  Markus Brunner, Mark Jonas
+ *
+ *  I/O addresses and bitmasks for Magic Panel Release 2 board
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_SH_MAGICPANELR2_H
+#define __ASM_SH_MAGICPANELR2_H
+
+#include <asm/gpio.h>
+
+#define __IO_PREFIX mpr2
+#include <asm/io_generic.h>
+
+
+#define SETBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) | mask, reg)
+#define SETBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) | mask, reg)
+#define SETBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) | mask, reg)
+#define CLRBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) & ~mask, reg)
+#define CLRBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) & ~mask, reg)
+#define CLRBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) & ~mask, reg)
+
+
+#define PA_LED          PORT_PADR      /* LED */
+
+
+/* BSC */
+#define CMNCR           0xA4FD0000UL
+#define CS0BCR          0xA4FD0004UL
+#define CS2BCR          0xA4FD0008UL
+#define CS3BCR          0xA4FD000CUL
+#define CS4BCR          0xA4FD0010UL
+#define CS5ABCR         0xA4FD0014UL
+#define CS5BBCR         0xA4FD0018UL
+#define CS6ABCR         0xA4FD001CUL
+#define CS6BBCR         0xA4FD0020UL
+#define CS0WCR          0xA4FD0024UL
+#define CS2WCR          0xA4FD0028UL
+#define CS3WCR          0xA4FD002CUL
+#define CS4WCR          0xA4FD0030UL
+#define CS5AWCR         0xA4FD0034UL
+#define CS5BWCR         0xA4FD0038UL
+#define CS6AWCR         0xA4FD003CUL
+#define CS6BWCR         0xA4FD0040UL
+
+
+/* usb */
+
+#define PORT_UTRCTL		0xA405012CUL
+#define PORT_UCLKCR_W		0xA40A0008UL
+
+#define INTC_ICR0		0xA414FEE0UL
+#define INTC_ICR1		0xA4140010UL
+#define INTC_ICR2		0xA4140012UL
+
+/* MTD */
+
+#define MPR2_MTD_BOOTLOADER_SIZE	0x00060000UL
+#define MPR2_MTD_KERNEL_SIZE		0x00200000UL
+
+#endif  /* __ASM_SH_MAGICPANELR2_H */
diff --git a/arch/sh/include/mach-common/mach/microdev.h b/arch/sh/include/mach-common/mach/microdev.h
new file mode 100644
index 000000000000..1aed15856e11
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/microdev.h
@@ -0,0 +1,80 @@
+/*
+ * linux/include/asm-sh/microdev.h
+ *
+ * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
+ *
+ * Definitions for the SuperH SH4-202 MicroDev board.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+#ifndef __ASM_SH_MICRODEV_H
+#define __ASM_SH_MICRODEV_H
+
+extern void init_microdev_irq(void);
+extern void microdev_print_fpga_intc_status(void);
+
+/*
+ * The following are useful macros for manipulating the interrupt
+ * controller (INTC) on the CPU-board FPGA.  should be noted that there
+ * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
+ * these are two different things, both of which need to be prorammed to
+ * correctly route - unfortunately, they have the same name and
+ * abbreviations!
+ */
+#define	MICRODEV_FPGA_INTC_BASE		0xa6110000ul				/* INTC base address on CPU-board FPGA */
+#define	MICRODEV_FPGA_INTENB_REG	(MICRODEV_FPGA_INTC_BASE+0ul)		/* Interrupt Enable Register on INTC on CPU-board FPGA */
+#define	MICRODEV_FPGA_INTDSB_REG	(MICRODEV_FPGA_INTC_BASE+8ul)		/* Interrupt Disable Register on INTC on CPU-board FPGA */
+#define	MICRODEV_FPGA_INTC_MASK(n)	(1ul<<(n))				/* Interrupt mask to enable/disable INTC in CPU-board FPGA */
+#define	MICRODEV_FPGA_INTPRI_REG(n)	(MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
+#define	MICRODEV_FPGA_INTPRI_LEVEL(n,x)	((x)<<(((n)%8)*4))			/* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
+#define	MICRODEV_FPGA_INTPRI_MASK(n)	(MICRODEV_FPGA_INTPRI_LEVEL((n),0xful))	/* Interrupt Priority Mask on INTC on CPU-board FPGA */
+#define	MICRODEV_FPGA_INTSRC_REG	(MICRODEV_FPGA_INTC_BASE+0x30ul)	/* Interrupt Source Register on INTC on CPU-board FPGA */
+#define	MICRODEV_FPGA_INTREQ_REG	(MICRODEV_FPGA_INTC_BASE+0x38ul)	/* Interrupt Request Register on INTC on CPU-board FPGA */
+
+
+/*
+ * The following are the IRQ numbers for the Linux Kernel for external
+ * interrupts.  i.e. the numbers seen by 'cat /proc/interrupt'.
+ */
+#define MICRODEV_LINUX_IRQ_KEYBOARD	 1	/* SuperIO Keyboard */
+#define MICRODEV_LINUX_IRQ_SERIAL1	 2	/* SuperIO Serial #1 */
+#define MICRODEV_LINUX_IRQ_ETHERNET	 3	/* on-board Ethnernet */
+#define MICRODEV_LINUX_IRQ_SERIAL2	 4	/* SuperIO Serial #2 */
+#define MICRODEV_LINUX_IRQ_USB_HC	 7	/* on-board USB HC */
+#define MICRODEV_LINUX_IRQ_MOUSE	12	/* SuperIO PS/2 Mouse */
+#define MICRODEV_LINUX_IRQ_IDE2		13	/* SuperIO IDE #2 */
+#define MICRODEV_LINUX_IRQ_IDE1		14	/* SuperIO IDE #1 */
+
+/*
+ * The following are the IRQ numbers for the INTC on the FPGA for
+ * external interrupts.  i.e. the bits in the INTC registers in the
+ * FPGA.
+ */
+#define MICRODEV_FPGA_IRQ_KEYBOARD	 1	/* SuperIO Keyboard */
+#define MICRODEV_FPGA_IRQ_SERIAL1	 3	/* SuperIO Serial #1 */
+#define MICRODEV_FPGA_IRQ_SERIAL2	 4	/* SuperIO Serial #2 */
+#define MICRODEV_FPGA_IRQ_MOUSE		12	/* SuperIO PS/2 Mouse */
+#define MICRODEV_FPGA_IRQ_IDE1		14	/* SuperIO IDE #1 */
+#define MICRODEV_FPGA_IRQ_IDE2		15	/* SuperIO IDE #2 */
+#define MICRODEV_FPGA_IRQ_USB_HC	16	/* on-board USB HC */
+#define MICRODEV_FPGA_IRQ_ETHERNET	18	/* on-board Ethnernet */
+
+#define MICRODEV_IRQ_PCI_INTA		 8
+#define MICRODEV_IRQ_PCI_INTB		 9
+#define MICRODEV_IRQ_PCI_INTC		10
+#define MICRODEV_IRQ_PCI_INTD		11
+
+#define __IO_PREFIX microdev
+#include <asm/io_generic.h>
+
+#if defined(CONFIG_PCI)
+unsigned char  microdev_pci_inb(unsigned long port);
+unsigned short microdev_pci_inw(unsigned long port);
+unsigned long  microdev_pci_inl(unsigned long port);
+void           microdev_pci_outb(unsigned char  data, unsigned long port);
+void           microdev_pci_outw(unsigned short data, unsigned long port);
+void           microdev_pci_outl(unsigned long  data, unsigned long port);
+#endif
+
+#endif /* __ASM_SH_MICRODEV_H */
diff --git a/arch/sh/include/mach-common/mach/migor.h b/arch/sh/include/mach-common/mach/migor.h
new file mode 100644
index 000000000000..e451f0229e00
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/migor.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_SH_MIGOR_H
+#define __ASM_SH_MIGOR_H
+
+/*
+ * linux/include/asm-sh/migor.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ *
+ * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* GPIO */
+#define PORT_PACR 0xa4050100
+#define PORT_PDCR 0xa4050106
+#define PORT_PECR 0xa4050108
+#define PORT_PHCR 0xa405010e
+#define PORT_PJCR 0xa4050110
+#define PORT_PKCR 0xa4050112
+#define PORT_PLCR 0xa4050114
+#define PORT_PMCR 0xa4050116
+#define PORT_PRCR 0xa405011c
+#define PORT_PTCR 0xa4050140
+#define PORT_PUCR 0xa4050142
+#define PORT_PVCR 0xa4050144
+#define PORT_PWCR 0xa4050146
+#define PORT_PXCR 0xa4050148
+#define PORT_PYCR 0xa405014a
+#define PORT_PZCR 0xa405014c
+#define PORT_PADR 0xa4050120
+#define PORT_PHDR 0xa405012e
+#define PORT_PTDR 0xa4050160
+#define PORT_PWDR 0xa4050166
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRC 0xa405015c
+
+#define PORT_MSELCRB 0xa4050182
+
+#define PORT_PSELA 0xa405014e
+#define PORT_PSELB 0xa4050150
+#define PORT_PSELC 0xa4050152
+#define PORT_PSELD 0xa4050154
+#define PORT_PSELE 0xa4050156
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRB 0xa405015a
+#define PORT_HIZCRC 0xa405015c
+
+#define BSC_CS4BCR 0xfec10010
+#define BSC_CS6ABCR 0xfec1001c
+#define BSC_CS4WCR 0xfec10030
+
+#include <video/sh_mobile_lcdc.h>
+
+int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
+			 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
+
+#endif /* __ASM_SH_MIGOR_H */
diff --git a/arch/sh/include/mach-common/mach/r2d.h b/arch/sh/include/mach-common/mach/r2d.h
new file mode 100644
index 000000000000..0a800157b826
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/r2d.h
@@ -0,0 +1,70 @@
+#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
+#define __ASM_SH_RENESAS_RTS7751R2D_H
+
+/*
+ * linux/include/asm-sh/renesas_rts7751r2d.h
+ *
+ * Copyright (C) 2000  Atom Create Engineering Co., Ltd.
+ *
+ * Renesas Technology Sales RTS7751R2D support
+ */
+
+/* Board specific addresses.  */
+
+#define PA_BCR		0xa4000000	/* FPGA */
+#define PA_IRLMON	0xa4000002	/* Interrupt Status control */
+#define PA_CFCTL	0xa4000004	/* CF Timing control */
+#define PA_CFPOW	0xa4000006	/* CF Power control */
+#define PA_DISPCTL	0xa4000008	/* Display Timing control */
+#define PA_SDMPOW	0xa400000a	/* SD Power control */
+#define PA_RTCCE	0xa400000c	/* RTC(9701) Enable control */
+#define PA_PCICD	0xa400000e	/* PCI Extention detect control */
+#define PA_VOYAGERRTS	0xa4000020	/* VOYAGER Reset control */
+
+#define PA_R2D1_AXRST		0xa4000022	/* AX_LAN Reset control */
+#define PA_R2D1_CFRST		0xa4000024	/* CF Reset control */
+#define PA_R2D1_ADMRTS		0xa4000026	/* SD Reset control */
+#define PA_R2D1_EXTRST		0xa4000028	/* Extention Reset control */
+#define PA_R2D1_CFCDINTCLR	0xa400002a	/* CF Insert Interrupt clear */
+
+#define PA_R2DPLUS_CFRST	0xa4000022	/* CF Reset control */
+#define PA_R2DPLUS_ADMRTS	0xa4000024	/* SD Reset control */
+#define PA_R2DPLUS_EXTRST	0xa4000026	/* Extention Reset control */
+#define PA_R2DPLUS_CFCDINTCLR	0xa4000028	/* CF Insert Interrupt clear */
+#define PA_R2DPLUS_KEYCTLCLR	0xa400002a	/* Key Interrupt clear */
+
+#define PA_POWOFF	0xa4000030	/* Board Power OFF control */
+#define PA_VERREG	0xa4000032	/* FPGA Version Register */
+#define PA_INPORT	0xa4000034	/* KEY Input Port control */
+#define PA_OUTPORT	0xa4000036	/* LED control */
+#define PA_BVERREG	0xa4000038	/* Board Revision Register */
+
+#define PA_AX88796L	0xaa000400	/* AX88796L Area */
+#define PA_VOYAGER	0xab000000	/* VOYAGER GX Area */
+#define PA_IDE_OFFSET	0x1f0		/* CF IDE Offset */
+#define AX88796L_IO_BASE	0x1000	/* AX88796L IO Base Address */
+
+#define IRLCNTR1	(PA_BCR + 0)	/* Interrupt Control Register1 */
+
+#define R2D_FPGA_IRQ_BASE	100
+
+#define IRQ_VOYAGER		(R2D_FPGA_IRQ_BASE + 0)
+#define IRQ_EXT			(R2D_FPGA_IRQ_BASE + 1)
+#define IRQ_TP			(R2D_FPGA_IRQ_BASE + 2)
+#define IRQ_RTC_T		(R2D_FPGA_IRQ_BASE + 3)
+#define IRQ_RTC_A		(R2D_FPGA_IRQ_BASE + 4)
+#define IRQ_SDCARD		(R2D_FPGA_IRQ_BASE + 5)
+#define IRQ_CF_CD		(R2D_FPGA_IRQ_BASE + 6)
+#define IRQ_CF_IDE		(R2D_FPGA_IRQ_BASE + 7)
+#define IRQ_AX88796		(R2D_FPGA_IRQ_BASE + 8)
+#define IRQ_KEY			(R2D_FPGA_IRQ_BASE + 9)
+#define IRQ_PCI_INTA		(R2D_FPGA_IRQ_BASE + 10)
+#define IRQ_PCI_INTB		(R2D_FPGA_IRQ_BASE + 11)
+#define IRQ_PCI_INTC		(R2D_FPGA_IRQ_BASE + 12)
+#define IRQ_PCI_INTD		(R2D_FPGA_IRQ_BASE + 13)
+
+/* arch/sh/boards/renesas/rts7751r2d/irq.c */
+void init_rts7751r2d_IRQ(void);
+int rts7751r2d_irq_demux(int);
+
+#endif  /* __ASM_SH_RENESAS_RTS7751R2D */
diff --git a/arch/sh/include/mach-common/mach/sdk7780.h b/arch/sh/include/mach-common/mach/sdk7780.h
new file mode 100644
index 000000000000..697dc865f21b
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sdk7780.h
@@ -0,0 +1,81 @@
+#ifndef __ASM_SH_RENESAS_SDK7780_H
+#define __ASM_SH_RENESAS_SDK7780_H
+
+/*
+ * linux/include/asm-sh/sdk7780.h
+ *
+ * Renesas Solutions SH7780 SDK Support
+ * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH	4		/* Area0: 32bit */
+#define PA_ROM			0xa0000000	/* EPROM */
+#define PA_ROM_SIZE		0x00400000	/* EPROM size 4M byte */
+#define PA_FROM			0xa0800000	/* Flash-ROM */
+#define PA_FROM_SIZE	0x00400000	/* Flash-ROM size 4M byte */
+#define PA_EXT1			0xa4000000
+#define PA_EXT1_SIZE	0x04000000
+#define PA_SDRAM		0xa8000000	/* DDR-SDRAM(Area2/3) 128MB */
+#define PA_SDRAM_SIZE	0x08000000
+
+#define PA_EXT4			0xb0000000
+#define PA_EXT4_SIZE	0x04000000
+#define PA_EXT_USER		PA_EXT4		/* User Expansion Space */
+
+#define PA_PERIPHERAL	PA_AREA5_IO
+
+/* SRAM/Reserved */
+#define PA_RESERVED	(PA_PERIPHERAL + 0)
+/* FPGA base address */
+#define PA_FPGA		(PA_PERIPHERAL + 0x01000000)
+/* SMC LAN91C111 */
+#define PA_LAN		(PA_PERIPHERAL + 0x01800000)
+
+
+#define FPGA_SRSTR      (PA_FPGA + 0x000)	/* System reset */
+#define FPGA_IRQ0SR     (PA_FPGA + 0x010)	/* IRQ0 status */
+#define FPGA_IRQ0MR     (PA_FPGA + 0x020)	/* IRQ0 mask */
+#define FPGA_BDMR       (PA_FPGA + 0x030)	/* Board operating mode */
+#define FPGA_INTT0PRTR  (PA_FPGA + 0x040)	/* Interrupt test mode0 port */
+#define FPGA_INTT0SELR  (PA_FPGA + 0x050)	/* Int. test mode0 select */
+#define FPGA_INTT1POLR  (PA_FPGA + 0x060)	/* Int. test mode0 polarity */
+#define FPGA_NMIR       (PA_FPGA + 0x070)	/* NMI source */
+#define FPGA_NMIMR      (PA_FPGA + 0x080)	/* NMI mask */
+#define FPGA_IRQR       (PA_FPGA + 0x090)	/* IRQX source */
+#define FPGA_IRQMR      (PA_FPGA + 0x0A0)	/* IRQX mask */
+#define FPGA_SLEDR      (PA_FPGA + 0x0B0)	/* LED control */
+#define PA_LED			FPGA_SLEDR
+#define FPGA_MAPSWR     (PA_FPGA + 0x0C0)	/* Map switch */
+#define FPGA_FPVERR     (PA_FPGA + 0x0D0)	/* FPGA version */
+#define FPGA_FPDATER    (PA_FPGA + 0x0E0)	/* FPGA date */
+#define FPGA_RSE        (PA_FPGA + 0x100)	/* Reset source */
+#define FPGA_EASR       (PA_FPGA + 0x110)	/* External area select */
+#define FPGA_SPER       (PA_FPGA + 0x120)	/* Serial port enable */
+#define FPGA_IMSR       (PA_FPGA + 0x130)	/* Interrupt mode select */
+#define FPGA_PCIMR      (PA_FPGA + 0x140)	/* PCI Mode */
+#define FPGA_DIPSWMR    (PA_FPGA + 0x150)	/* DIPSW monitor */
+#define FPGA_FPODR      (PA_FPGA + 0x160)	/* Output port data */
+#define FPGA_ATAESR     (PA_FPGA + 0x170)	/* ATA extended bus status */
+#define FPGA_IRQPOLR    (PA_FPGA + 0x180)	/* IRQx polarity */
+
+
+#define SDK7780_NR_IRL			15
+/* IDE/ATA interrupt */
+#define IRQ_CFCARD				14
+/* SMC interrupt */
+#define IRQ_ETHERNET			6
+
+
+/* arch/sh/boards/renesas/sdk7780/irq.c */
+void init_sdk7780_IRQ(void);
+
+#define __IO_PREFIX		sdk7780
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_RENESAS_SDK7780_H */
diff --git a/arch/sh/include/mach-common/mach/sh7763rdp.h b/arch/sh/include/mach-common/mach/sh7763rdp.h
new file mode 100644
index 000000000000..8750cc852977
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sh7763rdp.h
@@ -0,0 +1,54 @@
+#ifndef __ASM_SH_SH7763RDP_H
+#define __ASM_SH_SH7763RDP_H
+
+/*
+ * linux/include/asm-sh/sh7763drp.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* clock control */
+#define MSTPCR1 0xFFC80038
+
+/* PORT */
+#define PORT_PSEL0	0xFFEF0070
+#define PORT_PSEL1	0xFFEF0072
+#define PORT_PSEL2	0xFFEF0074
+#define PORT_PSEL3	0xFFEF0076
+#define PORT_PSEL4	0xFFEF0078
+
+#define PORT_PACR	0xFFEF0000
+#define PORT_PCCR	0xFFEF0004
+#define PORT_PFCR	0xFFEF000A
+#define PORT_PGCR	0xFFEF000C
+#define PORT_PHCR	0xFFEF000E
+#define PORT_PICR	0xFFEF0010
+#define PORT_PJCR	0xFFEF0012
+#define PORT_PKCR	0xFFEF0014
+#define PORT_PLCR	0xFFEF0016
+#define PORT_PMCR	0xFFEF0018
+#define PORT_PNCR	0xFFEF001A
+
+/* FPGA */
+#define CPLD_BOARD_ID_ERV_REG	0xB1000000
+#define CPLD_CPLD_CMD_REG		0xB1000006
+
+/*
+ * USB SH7763RDP board can use Host only.
+ */
+#define USB_USBHSC	0xFFEC80f0
+
+/* arch/sh/boards/renesas/sh7763rdp/irq.c */
+void init_sh7763rdp_IRQ(void);
+int sh7763rdp_irq_demux(int irq);
+#define __IO_PREFIX	sh7763rdp
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SH7763RDP_H */
diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
new file mode 100644
index 000000000000..1ce27d5c7491
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
@@ -0,0 +1,55 @@
+#ifndef __ASM_SH_RENESAS_SH7785LCR_H
+#define __ASM_SH_RENESAS_SH7785LCR_H
+
+/*
+ * This board has 2 physical memory maps.
+ * It can be changed with DIP switch(S2-5).
+ *
+ * phys address			| S2-5 = OFF	| S2-5 = ON
+ * -----------------------------+---------------+---------------
+ * 0x00000000 - 0x03ffffff(CS0)	| NOR Flash	| NOR Flash
+ * 0x04000000 - 0x05ffffff(CS1)	| PLD		| PLD
+ * 0x06000000 - 0x07ffffff(CS1)	| reserved	| I2C
+ * 0x08000000 - 0x0bffffff(CS2)	| USB		| DDR SDRAM
+ * 0x0c000000 - 0x0fffffff(CS3)	| SD		| DDR SDRAM
+ * 0x10000000 - 0x13ffffff(CS4)	| SM107		| SM107
+ * 0x14000000 - 0x17ffffff(CS5)	| I2C		| USB
+ * 0x18000000 - 0x1bffffff(CS6)	| reserved	| SD
+ * 0x40000000 - 0x5fffffff	| DDR SDRAM	| (cannot use)
+ *
+ */
+
+#define NOR_FLASH_ADDR		0x00000000
+#define NOR_FLASH_SIZE		0x04000000
+
+#define PLD_BASE_ADDR		0x04000000
+#define PLD_PCICR		(PLD_BASE_ADDR + 0x00)
+#define PLD_LCD_BK_CONTR	(PLD_BASE_ADDR + 0x02)
+#define PLD_LOCALCR		(PLD_BASE_ADDR + 0x04)
+#define PLD_POFCR		(PLD_BASE_ADDR + 0x06)
+#define PLD_LEDCR		(PLD_BASE_ADDR + 0x08)
+#define PLD_SWSR		(PLD_BASE_ADDR + 0x0a)
+#define PLD_VERSR		(PLD_BASE_ADDR + 0x0c)
+#define PLD_MMSR		(PLD_BASE_ADDR + 0x0e)
+
+#define SM107_MEM_ADDR		0x10000000
+#define SM107_MEM_SIZE		0x00e00000
+#define SM107_REG_ADDR		0x13e00000
+#define SM107_REG_SIZE		0x00200000
+
+#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
+#define R8A66597_ADDR		0x14000000	/* USB */
+#define CG200_ADDR		0x18000000	/* SD */
+#define PCA9564_ADDR		0x06000000	/* I2C */
+#else
+#define R8A66597_ADDR		0x08000000
+#define CG200_ADDR		0x0c000000
+#define PCA9564_ADDR		0x14000000
+#endif
+
+#define R8A66597_SIZE		0x00000100
+#define CG200_SIZE		0x00010000
+#define PCA9564_SIZE		0x00000100
+
+#endif  /* __ASM_SH_RENESAS_SH7785LCR_H */
+
diff --git a/arch/sh/include/mach-common/mach/shmin.h b/arch/sh/include/mach-common/mach/shmin.h
new file mode 100644
index 000000000000..36ba138a81fb
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/shmin.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_SH_SHMIN_H
+#define __ASM_SH_SHMIN_H
+
+#define SHMIN_IO_BASE 0xb0000000UL
+
+#define SHMIN_NE_IRQ IRQ2_IRQ
+#define SHMIN_NE_BASE 0x300
+
+#endif
diff --git a/arch/sh/include/mach-common/mach/snapgear.h b/arch/sh/include/mach-common/mach/snapgear.h
new file mode 100644
index 000000000000..042d95f51c4d
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/snapgear.h
@@ -0,0 +1,71 @@
+/*
+ * include/asm-sh/snapgear.h
+ *
+ * Modified version of io_se.h for the snapgear-specific functions.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * IO functions for a SnapGear
+ */
+
+#ifndef _ASM_SH_IO_SNAPGEAR_H
+#define _ASM_SH_IO_SNAPGEAR_H
+
+#if defined(CONFIG_CPU_SH4)
+/*
+ * The external interrupt lines, these take up ints 0 - 15 inclusive
+ * depending on the priority for the interrupt.  In fact the priority
+ * is the interrupt :-)
+ */
+
+#define IRL0_IRQ	2
+#define IRL0_PRIORITY	13
+
+#define IRL1_IRQ	5
+#define IRL1_PRIORITY	10
+
+#define IRL2_IRQ	8
+#define IRL2_PRIORITY	7
+
+#define IRL3_IRQ	11
+#define IRL3_PRIORITY	4
+#endif
+
+#define __IO_PREFIX	snapgear
+#include <asm/io_generic.h>
+
+#ifdef CONFIG_SH_SECUREEDGE5410
+/*
+ * We need to remember what was written to the ioport as some bits
+ * are shared with other functions and you cannot read back what was
+ * written :-|
+ *
+ * Bit        Read                   Write
+ * -----------------------------------------------
+ * D0         DCD on ttySC1          power
+ * D1         Reset Switch           heatbeat
+ * D2         ttySC0 CTS (7100)      LAN
+ * D3         -                      WAN
+ * D4         ttySC0 DCD (7100)      CONSOLE
+ * D5         -                      ONLINE
+ * D6         -                      VPN
+ * D7         -                      DTR on ttySC1
+ * D8         -                      ttySC0 RTS (7100)
+ * D9         -                      ttySC0 DTR (7100)
+ * D10        -                      RTC SCLK
+ * D11        RTC DATA               RTC DATA
+ * D12        -                      RTS RESET
+ */
+
+#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000)
+extern unsigned short secureedge5410_ioport;
+
+#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \
+	 (secureedge5410_ioport = \
+			((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
+#define SECUREEDGE_READ_IOPORT() \
+	 ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
+#endif
+
+#endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/arch/sh/include/mach-common/mach/systemh7751.h b/arch/sh/include/mach-common/mach/systemh7751.h
new file mode 100644
index 000000000000..4161122c84ef
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/systemh7751.h
@@ -0,0 +1,71 @@
+#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
+#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
+
+/*
+ * linux/include/asm-sh/systemh/7751systemh.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SystemH support
+
+ * Modified for 7751 SystemH by
+ * Jonathan Short, 2002.
+ */
+
+/* Box specific addresses.  */
+
+#define PA_ROM		0x00000000	/* EPROM */
+#define PA_ROM_SIZE	0x00400000	/* EPROM size 4M byte */
+#define PA_FROM		0x01000000	/* EPROM */
+#define PA_FROM_SIZE	0x00400000	/* EPROM size 4M byte */
+#define PA_EXT1		0x04000000
+#define PA_EXT1_SIZE	0x04000000
+#define PA_EXT2		0x08000000
+#define PA_EXT2_SIZE	0x04000000
+#define PA_SDRAM	0x0c000000
+#define PA_SDRAM_SIZE	0x04000000
+
+#define PA_EXT4		0x12000000
+#define PA_EXT4_SIZE	0x02000000
+#define PA_EXT5		0x14000000
+#define PA_EXT5_SIZE	0x04000000
+#define PA_PCIC		0x18000000	/* MR-SHPC-01 PCMCIA */
+
+#define PA_DIPSW0	0xb9000000	/* Dip switch 5,6 */
+#define PA_DIPSW1	0xb9000002	/* Dip switch 7,8 */
+#define PA_LED		0xba000000	/* LED */
+#define	PA_BCR		0xbb000000	/* FPGA on the MS7751SE01 */
+
+#define PA_MRSHPC	0xb83fffe0	/* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1	0xb8400000	/* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2	0xb8500000	/* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO	0xb8600000	/* MR-SHPC-01 I/O window base */
+#define MRSHPC_MODE     (PA_MRSHPC + 4)
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA	(PA_BCR + 0)
+#define BCR_ILCRB	(PA_BCR + 2)
+#define BCR_ILCRC	(PA_BCR + 4)
+#define BCR_ILCRD	(PA_BCR + 6)
+#define BCR_ILCRE	(PA_BCR + 8)
+#define BCR_ILCRF	(PA_BCR + 10)
+#define BCR_ILCRG	(PA_BCR + 12)
+
+#define IRQ_79C973	13
+
+#define __IO_PREFIX	sh7751systemh
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
diff --git a/arch/sh/include/mach-common/mach/titan.h b/arch/sh/include/mach-common/mach/titan.h
new file mode 100644
index 000000000000..03f3583c8918
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/titan.h
@@ -0,0 +1,17 @@
+/*
+ * Platform defintions for Titan
+ */
+#ifndef _ASM_SH_TITAN_H
+#define _ASM_SH_TITAN_H
+
+#define __IO_PREFIX titan
+#include <asm/io_generic.h>
+
+/* IRQ assignments */
+#define TITAN_IRQ_WAN		2	/* eth0 (WAN) */
+#define TITAN_IRQ_LAN		5	/* eth1 (LAN) */
+#define TITAN_IRQ_MPCIA		8	/* mPCI A */
+#define TITAN_IRQ_MPCIB		11	/* mPCI B */
+#define TITAN_IRQ_USB		11	/* USB */
+
+#endif /* __ASM_SH_TITAN_H */