diff options
| author | Chris Metcalf <cmetcalf@tilera.com> | 2012-03-29 15:23:54 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2012-04-02 12:12:52 -0400 |
| commit | a714ffff36a581756ec3b001f47e8e5e96a9fa0e (patch) | |
| tree | 73f84f87b09b30f9621f50748b897303bb1d3b6a /arch/tile/kernel/intvec_64.S | |
| parent | e17235382dbb05f70146e141e4b780fd069050dc (diff) | |
arch/tile: fix up some minor trap handling issues
We now respond to MEM_ERROR traps (e.g. an atomic instruction to
non-cacheable memory) with a SIGBUS.
We also no longer generate a console crash message if a user
process die due to a SIGTRAP.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel/intvec_64.S')
| -rw-r--r-- | arch/tile/kernel/intvec_64.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S index 2c181c864ef7..005535d108c1 100644 --- a/arch/tile/kernel/intvec_64.S +++ b/arch/tile/kernel/intvec_64.S @@ -1178,7 +1178,7 @@ STD_ENTRY(fill_ra_stack) #define do_hardwall_trap bad_intr #endif - int_hand INT_MEM_ERROR, MEM_ERROR, bad_intr + int_hand INT_MEM_ERROR, MEM_ERROR, do_trap int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr #if CONFIG_KERNEL_PL == 2 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle |