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authorweiyi.lu@mediatek.com <weiyi.lu@mediatek.com>2017-10-23 12:10:34 +0800
committerStephen Boyd <sboyd@codeaurora.org>2017-11-02 01:02:53 -0700
commite2f744a82d725ab55091cccfb8e527b4220471f0 (patch)
tree7e8776522ae45675ad1d48c52f25092facd97a0b /drivers/clk/mediatek/clk-mtk.h
parentb7f1a721bb3e493627d9db0a00edfb53c70ba823 (diff)
clk: mediatek: Add MT2712 clock support
Add MT2712 clock support, include topckgen, apmixedsys, infracfg, pericfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> [sboyd@codeaurora.org: Static on top_clk_data] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.h')
-rw-r--r--drivers/clk/mediatek/clk-mtk.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f5d6b70ce189..f48df75cc901 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -207,6 +207,8 @@ struct mtk_pll_data {
uint32_t en_mask;
uint32_t pd_reg;
uint32_t tuner_reg;
+ uint32_t tuner_en_reg;
+ uint8_t tuner_en_bit;
int pd_shift;
unsigned int flags;
const struct clk_ops *ops;