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authorClaudiu Beznea <claudiu.beznea@microchip.com>2021-10-11 14:27:14 +0300
committerStephen Boyd <sboyd@kernel.org>2021-10-26 18:27:43 -0700
commit0ef99f8202c5078a72c05af76bfaed2ea4daab19 (patch)
tree6a2d76aaa74d430fd4bc51ac1345c491a78b1c8c /drivers/clk
parenta27748adeacab6e1fa957cdc4838f3cdedce3ce5 (diff)
clk: at91: clk-master: fix prescaler logic
When prescaler value read from register is MASTER_PRES_MAX it means that the input clock will be divided by 3. Fix the code to reflect this. Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/at91/clk-master.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 6da9ae34313a..e67bcd03a827 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
val &= master->layout->mask;
pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
- if (pres == 3 && characteristics->have_div3_pres)
+ if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
pres = 3;
else
pres = (1 << pres);