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authorBen Widawsky <ben.widawsky@intel.com>2022-01-23 16:29:53 -0800
committerDan Williams <dan.j.williams@intel.com>2022-02-08 22:57:29 -0800
commit53fa1bff3426344d466d91e81f076eab677d0ece (patch)
treee29317f8652ba42a4da2a3b98d90c11d6b65865c /drivers/cxl/core
parentd2b61ed2ff63fd9f294db8399c7a680ea7fe8a23 (diff)
cxl/core: Track port depth
In preparation for proving CXL subsystem usage of the device_lock() order track the depth of ports with the expectation that shallower port locks can be held over deeper port locks. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/core')
-rw-r--r--drivers/cxl/core/port.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 73ff42a05473..f287d87da6d6 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -362,6 +362,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
if (IS_ERR(port))
return port;
+ if (parent_port)
+ port->depth = parent_port->depth + 1;
dev = &port->dev;
if (parent_port)
rc = dev_set_name(dev, "port%d", port->id);