diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2017-11-13 15:45:31 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 12:47:47 -0500 |
| commit | adfb81659cb5c6f781924601462336166fe17174 (patch) | |
| tree | e3b5a07eb7ea2aac31226cdd7ec1448d4572a7c4 /drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |
| parent | 93442184c0dd3a7e714eb117038e985e9355a9df (diff) | |
drm/amdgpu/gfx7: use cached values for raster config in clear state
Use the cached values rather than hardcoding it.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 |
1 files changed, 2 insertions, 23 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 015f37bef358..83d94c23aa78 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2551,29 +2551,8 @@ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - switch (adev->asic_type) { - case CHIP_BONAIRE: - amdgpu_ring_write(ring, 0x16000012); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_KAVERI: - amdgpu_ring_write(ring, 0x00000000); /* XXX */ - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_KABINI: - case CHIP_MULLINS: - amdgpu_ring_write(ring, 0x00000000); /* XXX */ - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_HAWAII: - amdgpu_ring_write(ring, 0x3a00161a); - amdgpu_ring_write(ring, 0x0000002e); - break; - default: - amdgpu_ring_write(ring, 0x00000000); - amdgpu_ring_write(ring, 0x00000000); - break; - } + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); |