diff options
| author | Charlene Liu <charlene.liu@amd.com> | 2019-07-02 14:04:35 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:27:25 -0500 |
| commit | 39bca3599aab8edbc4a6c6d10fc76b1a932e5dfa (patch) | |
| tree | f16ce8c4e1cdf7776c7d120003c741d13a690902 /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20 | |
| parent | 54eef8a411699779fdbb1a2cd333f1b914bd5699 (diff) | |
drm/amd/display: add a option to force the clock at every mode change.
[Description]
This is for HW negative stress testing use.
force reset the dispclk and dppclk even the same clock already set in HW.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 9a873e2b3736..3cff4f0518d3 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -151,7 +151,14 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, bool enter_display_off = false; bool dpp_clock_lowered = false; struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; + bool force_reset = false; + if (clk_mgr_base->clks.dispclk_khz == 0 || + dc->debug.force_clock_mode & 0x1) { + //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. + force_reset = true; + //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. + } display_count = clk_mgr_helper_get_active_display_cnt(dc, context); if (dc->res_pool->pp_smu) pp_smu = &dc->res_pool->pp_smu->nv_funcs; @@ -223,7 +230,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, update_dispclk = true; } - if (dc->config.forced_clocks == false) { + if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { if (dpp_clock_lowered) { // if clock is being lowered, increase DTO before lowering refclk dcn20_update_clocks_update_dpp_dto(clk_mgr, context); |