diff options
| author | Jacky Liao <ziyu.liao@amd.com> | 2020-11-16 17:04:35 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-12-01 16:03:40 -0500 |
| commit | d0274aba24bf98aad04beb917dea4fbe45659a79 (patch) | |
| tree | e0638fd7d8db0bbdb47d9c465923c26fa71af0ee /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | |
| parent | 99349a8aeda7a044fc5850924bc3b57c306a1553 (diff) | |
drm/amd/display: Add DSCL memory low power support
[Why]
The DSCL memory blocks should be powered down when they're not in use.
This will reduce power consumption.
[How]
1. Write to DSCL_MEM_PWR_FORCE to put memory to shutdown when DSCL is not
used.
2. Added a debug option to allow this behaviour to be turned off
Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 2edf566b3a72..9a1f40eb5c47 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -51,6 +51,8 @@ SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\ SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ + SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \ + SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \ SRI(OTG_H_BLANK, DSCL, id), \ SRI(OTG_V_BLANK, DSCL, id), \ SRI(SCL_MODE, DSCL, id), \ @@ -252,6 +254,8 @@ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ + TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh), \ + TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh), \ TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ @@ -536,6 +540,8 @@ type SCL_V_INIT_INT_BOT_C; \ type SCL_CHROMA_COEF_MODE; \ type SCL_COEF_RAM_SELECT_CURRENT; \ + type LUT_MEM_PWR_FORCE; \ + type LUT_MEM_PWR_STATE; \ type CM_GAMUT_REMAP_MODE; \ type CM_GAMUT_REMAP_C11; \ type CM_GAMUT_REMAP_C12; \ @@ -1096,6 +1102,8 @@ struct dcn_dpp_mask { uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \ uint32_t OTG_H_BLANK; \ uint32_t OTG_V_BLANK; \ + uint32_t DSCL_MEM_PWR_CTRL; \ + uint32_t DSCL_MEM_PWR_STATUS; \ uint32_t SCL_MODE; \ uint32_t LB_DATA_FORMAT; \ uint32_t LB_MEMORY_CTRL; \ |