diff options
| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2017-07-20 14:51:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:25 -0400 |
| commit | 9b1c9b4c2eec7cb2a4d3762da7aa78aea8e34630 (patch) | |
| tree | df69dd9f57af654cc182fd1a1b30aebcf1b9c422 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | |
| parent | 2b13d7d380d50811fd4fc022d135c3c5bb70a418 (diff) | |
drm/amd/display: update dcn register headers
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h index f14e208dbf1c..69db441e78c4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h @@ -87,7 +87,6 @@ SRI(CM_DGAM_CONTROL, CM, id), \ SRI(FORMAT_CONTROL, CNVC_CFG, id), \ SRI(DPP_CONTROL, DPP_TOP, id), \ - SRI(CURSOR_SETTINS, HUBPREQ, id), \ SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ SRI(CURSOR0_CONTROL, CNVC_CUR, id), \ SRI(CURSOR0_COLOR0, CNVC_CUR, id), \ @@ -95,6 +94,7 @@ #define IPP_REG_LIST_DCN10(id) \ IPP_REG_LIST_DCN(id), \ + SRI(CURSOR_SETTINS, HUBPREQ, id), \ SRI(CM_IGAM_CONTROL, CM, id), \ SRI(CM_COMA_C11_C12, CM, id), \ SRI(CM_COMA_C13_C14, CM, id), \ @@ -240,8 +240,6 @@ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ - IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ - IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ @@ -250,6 +248,8 @@ #define IPP_MASK_SH_LIST_DCN10(mask_sh) \ IPP_MASK_SH_LIST_DCN(mask_sh),\ + IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ + IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh), \ IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh), \ IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh), \ @@ -537,6 +537,7 @@ struct dcn10_ipp_registers { uint32_t CM_IGAM_CONTROL; uint32_t DPP_CONTROL; uint32_t CURSOR_SETTINS; + uint32_t CURSOR_SETTINGS; uint32_t CNVC_SURFACE_PIXEL_FORMAT; uint32_t CURSOR0_CONTROL; uint32_t CURSOR0_COLOR0; |