diff options
| author | Tony Cheng <tony.cheng@amd.com> | 2017-07-12 22:00:34 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:23 -0400 |
| commit | fc0956909f24d2cd6f69777881bcccd771a06f35 (patch) | |
| tree | 8513382c16d3cd72af8bd50681c7450e82bb3156 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | |
| parent | 72f0281d34b464121f9f6b75a2d7a2502055ec79 (diff) | |
drm/amd/display: register programming consolidation
remove redundant DPP_CLOCK_ENABLE in ipp. clock programmed by HWSS
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h index 1703589623b0..f14e208dbf1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h @@ -235,7 +235,6 @@ IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ - IPP_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \ @@ -433,7 +432,6 @@ type CM_DGAM_LUT_WRITE_SEL; \ type CM_DGAM_LUT_INDEX; \ type CM_DGAM_LUT_DATA; \ - type DPP_CLOCK_ENABLE; \ type CM_BYPASS_EN; \ type CM_BYPASS; \ type CNVC_SURFACE_PIXEL_FORMAT; \ |