diff options
| author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-05-22 14:38:38 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:14 -0400 |
| commit | be547111d2be16e81dc2d9669cf3caa3675fa55d (patch) | |
| tree | 8e80801db274cca084dd7962ed735acb40979ef9 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | |
| parent | 7c40270be76d0ee33455bba728d508f5dddfc604 (diff) | |
drm/amd/display: Add DCN3 DIO
Add support for the DIO (Display IO) block of DCN3, which entails our
stream and link encoders.
HW Blocks:
+--------+
| DIO |
+--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h index 68395bcc24fd..cf59ab0034dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h @@ -153,6 +153,12 @@ struct dcn10_link_enc_registers { uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3; uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2; uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + uint32_t TMDS_DCBALANCER_CONTROL; + uint32_t PHYA_LINK_CNTL2; + uint32_t PHYB_LINK_CNTL2; + uint32_t PHYC_LINK_CNTL2; +#endif }; #define LE_SF(reg_name, field_name, post_fix)\ |