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authorAnthony Koo <Anthony.Koo@amd.com>2017-07-06 14:27:49 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 18:08:42 -0400
commit87449a90c2545eaed5757153770346563378463b (patch)
tree99f1389e2a1664b84151d690d0e5765cafea1640 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
parent184debdbd80bd9d47eb68304417adb6580ff09e4 (diff)
drm/amd/display: Fix MPO visual confirm
1. Need to blend non-active area to show visual confirm borders 2. Set number of Visual Confirm lines based on pipe instance 3. Set Different colors representing surface format of bottom most plan Signed-off-by: Anthony Koo <anthony.koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 7af04bce3599..1c9d5e96ab55 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -25,6 +25,7 @@
#include "reg_helper.h"
#include "dcn10_mpc.h"
+#include "dc.h"
#define REG(reg)\
mpcc10->mpcc_regs->reg
@@ -85,6 +86,8 @@ static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg)
BLND_PP_ALPHA : BLND_GLOBAL_ALPHA;
int mpcc_mode = cfg->bot_mpcc_id != 0xf ?
MODE_BLEND : MODE_TOP_ONLY;
+ bool blend_active_only = cfg->top_of_tree &&
+ !mpcc->ctx->dc->debug.surface_visual_confirm;
REG_SET(MPCC_OPP_ID, 0,
MPCC_OPP_ID, cfg->opp_id);
@@ -99,7 +102,7 @@ static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg)
MPCC_MODE, mpcc_mode,
MPCC_ALPHA_BLND_MODE, alpha_blnd_mode,
MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha,
- MPCC_BLND_ACTIVE_OVERLAP_ONLY, cfg->top_of_tree);
+ MPCC_BLND_ACTIVE_OVERLAP_ONLY, blend_active_only);
if (cfg->top_of_tree) {
if (cfg->opp_id != 0xf)