diff options
| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2017-06-14 18:58:04 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:08:22 -0400 |
| commit | cfe4645e17f8dbe680c35c439d000313f2648482 (patch) | |
| tree | 24730e43ae060acc6dc6db3eab85ac8e584d5d82 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | |
| parent | 7f524a0d838d8d9334003b956b73729f27a1315a (diff) | |
drm/amd/display: fix dcn pipe reset sequence
This change fixes dcn10 front end reset sequence. Previously we
would reset front end during flip which led to issues
in certain MPO and 4k/5k scenarios. We would also never properly
power gate our front end.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index b1c590d4f454..7af04bce3599 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -65,17 +65,17 @@ void dcn10_mpcc_set_bg_color( static void set_output_mux(struct dcn10_mpcc *mpcc10, int opp_id, int mpcc_id) { - ASSERT(mpcc10->opp_id == 0xf || opp_id == mpcc10->opp_id); - mpcc10->opp_id = opp_id; + ASSERT(mpcc10->base.opp_id == 0xf || opp_id == mpcc10->base.opp_id); + mpcc10->base.opp_id = opp_id; REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 1); REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id); } static void reset_output_mux(struct dcn10_mpcc *mpcc10) { - REG_SET(MUX[mpcc10->opp_id], 0, MPC_OUT_MUX, 0xf); - REG_UPDATE(OPP_PIPE_CONTROL[mpcc10->opp_id], OPP_PIPE_CLOCK_EN, 0); - mpcc10->opp_id = 0xf; + REG_SET(MUX[mpcc10->base.opp_id], 0, MPC_OUT_MUX, 0xf); + REG_UPDATE(OPP_PIPE_CONTROL[mpcc10->base.opp_id], OPP_PIPE_CLOCK_EN, 0); + mpcc10->base.opp_id = 0xf; } static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) @@ -104,16 +104,17 @@ static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) if (cfg->top_of_tree) { if (cfg->opp_id != 0xf) set_output_mux(mpcc10, cfg->opp_id, mpcc->inst); - else + else if (mpcc->opp_id != 0xf) reset_output_mux(mpcc10); } + mpcc10->base.opp_id = cfg->opp_id; } static void dcn10_mpcc_wait_idle(struct mpcc *mpcc) { struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc); - REG_WAIT(MPCC_STATUS, MPCC_IDLE, 1, 1000, 1000); + REG_WAIT(MPCC_STATUS, MPCC_BUSY, 0, 1000, 1000); } @@ -139,5 +140,5 @@ void dcn10_mpcc_construct(struct dcn10_mpcc *mpcc10, mpcc10->mpcc_shift = mpcc_shift; mpcc10->mpcc_mask = mpcc_mask; - mpcc10->opp_id = inst; + mpcc10->base.opp_id = inst; } |