diff options
| author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-05-21 12:43:28 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:14 -0400 |
| commit | 64e7f91e7ac88e94302a213cf61afe70b734fa2a (patch) | |
| tree | 5f569076b891b62323e6e8c958f32ab74974377e /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | |
| parent | 2a3a0d5d7962628684bb5cf4be38747dcbb1f35e (diff) | |
drm/amd/display: Add DCN3 OPTC
Add support for programming the DCN3 OPTC (Output Timing Controller)
HW Blocks:
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c index ec0ab42becba..43d0b4e53b5d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c @@ -288,8 +288,16 @@ void optc1_program_timing( if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) h_div = H_TIMING_DIV_BY2; - REG_UPDATE(OTG_H_TIMING_CNTL, + if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { + if (optc1->opp_count == 4) + h_div = H_TIMING_DIV_BY4; + + REG_UPDATE(OTG_H_TIMING_CNTL, + OTG_H_TIMING_DIV_MODE, h_div); + } else { + REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, h_div); + } } void optc1_set_vtg_params(struct timing_generator *optc, |