diff options
| author | Hyungwon Hwang <human.hwang@samsung.com> | 2015-04-10 10:39:01 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:43:25 +0900 |
| commit | 82b497929a3820151f0f07e46f2d1a900c485e0e (patch) | |
| tree | f03751c94f9a1d1b248b0298f5beaa189a3b8006 /drivers/gpu/drm/exynos/exynos_drm_dsi.c | |
| parent | e85f4651cebb5535e405a0167a4a28ddd88f944d (diff) | |
drm/exynos: dsi: add the backward compatibility for the renamed clock
From the commit a45abd04a46048a4956408543cdbdd8bdedd3215
("drm/exynos: dsi: rename pll_clk to sclk_clk'), the compiled dtb
which contains 'pll_clk' becomes not compatible with the current DSI
driver. This patch adds the backward compatibility for this issue.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_dsi.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 9b6fd4673422..6f948bdeb855 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -210,6 +210,8 @@ #define DSI_WRITE(dsi, reg, val) writel((val), REG((dsi), (reg))) #define DSI_READ(dsi, reg) readl(REG((dsi), (reg))) +#define OLD_SCLK_MIPI_CLK_NAME "pll_clk" + static char *clk_names[5] = { "bus_clk", "sclk_mipi", "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", "sclk_rgb_vclk_to_dsim0" }; @@ -1878,6 +1880,12 @@ static int exynos_dsi_probe(struct platform_device *pdev) for (i = 0; i < dsi->driver_data->num_clks; i++) { dsi->clks[i] = devm_clk_get(dev, clk_names[i]); if (IS_ERR(dsi->clks[i])) { + if (strcmp(clk_names[i], "sclk_mipi") == 0) { + strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); + i--; + continue; + } + dev_info(dev, "failed to get the clock: %s\n", clk_names[i]); ret = PTR_ERR(dsi->clks[i]); |