diff options
| author | Hyungwon Hwang <human.hwang@samsung.com> | 2015-05-21 18:00:49 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:45:11 +0900 |
| commit | b1e7866b56934863c7a713a8ab19ef707289ca90 (patch) | |
| tree | 8119285de1d261c08e20cd62368c43df5103ef6c /drivers/gpu/drm/exynos/exynos_drm_dsi.c | |
| parent | 2f5e054af19d88745727211a305deb68e75ecc38 (diff) | |
drm/exynos: dsi: enable lanes before configuring the lanes' clock
Function reset doesn't reset the configuration for lanes, so dsi could be
configured inappropriately when it turns on. So the lanes must be enabled
properly before configuring the clocks of them.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_dsi.c | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 74ab06855fc5..9feb2c10ba71 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -738,6 +738,14 @@ static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); } +static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) +{ + u32 reg = DSI_READ(dsi, DSIM_CONFIG_REG); + reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | + DSIM_LANE_EN(lane)); + DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); +} + static int exynos_dsi_init_link(struct exynos_dsi *dsi) { struct exynos_dsi_driver_data *driver_data = dsi->driver_data; @@ -810,17 +818,6 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi) return -EINVAL; } - reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1); - - DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); - - reg |= DSIM_LANE_EN_CLK; - DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); - - lanes_mask = BIT(dsi->lanes) - 1; - reg |= DSIM_LANE_EN(lanes_mask); - DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); - /* * Use non-continuous clock mode if the periparal wants and * host controller supports @@ -832,8 +829,11 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi) if (driver_data->has_clklane_stop && dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { reg |= DSIM_CLKLANE_STOP; - DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); } + DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); + + lanes_mask = BIT(dsi->lanes) - 1; + exynos_dsi_enable_lane(dsi, lanes_mask); /* Check clock and data lane state are stop state */ timeout = 100; @@ -1296,6 +1296,10 @@ static int exynos_dsi_init(struct exynos_dsi *dsi) exynos_dsi_reset(dsi); exynos_dsi_enable_irq(dsi); + + if (driver_data->values[RESET_TYPE] == DSIM_FUNCRST) + exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); + exynos_dsi_enable_clock(dsi); if (driver_data->wait_for_reset) exynos_dsi_wait_for_reset(dsi); |