diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-04-21 18:34:00 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-04-26 23:56:41 +0300 |
| commit | 924ad0e848b58cc492373d2d5fe9dcc0da0b9c6c (patch) | |
| tree | 7fbf9c201d662f06608dda17d2ef55ea29daa47e /drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | |
| parent | f765a5b48c667bdada5e49d5e0f23f8c0687b21b (diff) | |
drm/i915: Give C0DRB3/C1DRB3 a _BW suffix
These are the 965g/g45/g33 specific DRB registers. Give them
a suitable suffix so we can add their counterparts for other
platforms.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-4-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 8a322594210c..0fa6c38893f7 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) * banks of memory are paired and unswizzled on the * uneven portion, so leave that as unknown. */ - if (intel_uncore_read16(uncore, C0DRB3) == - intel_uncore_read16(uncore, C1DRB3)) { + if (intel_uncore_read16(uncore, C0DRB3_BW) == + intel_uncore_read16(uncore, C1DRB3_BW)) { swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_y = I915_BIT_6_SWIZZLE_9; } |