diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-04-21 18:33:59 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-04-26 23:56:34 +0300 |
| commit | f765a5b48c667bdada5e49d5e0f23f8c0687b21b (patch) | |
| tree | 0a3a3475eac7bd4f20d42a1e795e1aaffb692355 /drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | |
| parent | ed52c62d386f764194e0184fdb905d5f24194cae (diff) | |
drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
We've defined C0DRB3/C1DRB3 as 16 bit registers, so access them
as such.
Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-3-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index e72b7a0dc316..8a322594210c 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) * banks of memory are paired and unswizzled on the * uneven portion, so leave that as unknown. */ - if (intel_uncore_read(uncore, C0DRB3) == - intel_uncore_read(uncore, C1DRB3)) { + if (intel_uncore_read16(uncore, C0DRB3) == + intel_uncore_read16(uncore, C1DRB3)) { swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_y = I915_BIT_6_SWIZZLE_9; } |