diff options
| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2022-05-23 09:34:47 +0100 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2022-05-23 09:34:47 +0100 |
| commit | 8ec5c0006c50cb1909c0de0fad137909c1218990 (patch) | |
| tree | b5df17cb06943792b3a2c9f3fab8a2c357113b34 /drivers/gpu/drm/i915/gt/intel_rps.c | |
| parent | 39921e5f00f5a98ff9cb3229937ca339e8d9c9c6 (diff) | |
| parent | 5f38c3fb55ce3814b4353320d7a205068a420e48 (diff) | |
Merge tag 'drm-intel-next-2022-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-intel-gt-next
drm/i915 drm-intel-next -> drm-intel-gt-next cross-merge sync
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
# Conflicts:
# drivers/gpu/drm/i915/gt/intel_rps.c
# drivers/gpu/drm/i915/i915_vma.c
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87y1ywbh5y.fsf@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_rps.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_rps.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 3bd8415a0f1b..fb3f57ee450b 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1144,7 +1144,8 @@ static void gen6_rps_init(struct intel_rps *rps) if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) mult = GEN9_FREQ_SCALER; - if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, + if (snb_pcode_read(rps_to_gt(rps)->uncore, + HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, &ddcc_status, NULL) == 0) rps->efficient_freq = clamp_t(u32, @@ -1984,7 +1985,7 @@ void intel_rps_init(struct intel_rps *rps) if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) { u32 params = 0; - snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL); + snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_READ_OC_PARAMS, ¶ms, NULL); if (params & BIT(31)) { /* OC supported */ drm_dbg(&i915->drm, "Overclocking supported, max: %dMHz, overclock: %dMHz\n", |