diff options
| author | Vinay Belgaumkar <vinay.belgaumkar@intel.com> | 2021-12-16 15:30:22 -0800 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2021-12-21 11:24:55 -0800 |
| commit | 1c40d40f6835cdee99c6966b48b98d0e38c35f47 (patch) | |
| tree | 5cc9f5472c02425eff9963109aeec239466fe2e0 /drivers/gpu/drm/i915/gt/intel_rps.h | |
| parent | d8be1357edc891b4259e3ecc1b831452361379ac (diff) | |
drm/i915/guc: Request RP0 before loading firmware
By default, GT (and GuC) run at RPn. Requesting for RP0
before firmware load can speed up DMA and HuC auth as well.
In addition to writing to 0xA008, we also need to enable
swreq in 0xA024 so that Punit will pay heed to our request.
SLPC will restore the frequency back to RPn after initialization,
but we need to manually do that for the non-SLPC path.
We don't need a manual override in the SLPC disabled case, just
use the intel_rps_set function to ensure consistent RPS state.
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211216233022.21351-1-vinay.belgaumkar@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_rps.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_rps.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h index aee12f37d38a..c6d76a3d1331 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.h +++ b/drivers/gpu/drm/i915/gt/intel_rps.h @@ -45,6 +45,8 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); u32 intel_rps_read_punit_req(struct intel_rps *rps); u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); u32 intel_rps_read_state_cap(struct intel_rps *rps); +void intel_rps_raise_unslice(struct intel_rps *rps); +void intel_rps_lower_unslice(struct intel_rps *rps); void gen5_rps_irq_handler(struct intel_rps *rps); void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir); |