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authorJordan Crouse <jcrouse@codeaurora.org>2017-05-08 14:35:03 -0600
committerRob Clark <robdclark@gmail.com>2017-06-16 11:16:00 -0400
commit5770fc7a562e7da37cbf981f352d774c0142d7ba (patch)
tree3344505c979b2f166e1ba712496c05d68b9cbcbe /drivers/gpu/drm/msm/msm_gpu.h
parent49fd08baa36ac10b13ea7b23fc6bbee8b4a6fcfe (diff)
drm/msm: Add a struct to pass configuration to msm_gpu_init()
The amount of information that we need to pass into msm_gpu_init() is steadily increasing, so add a new struct to stabilize the function call and make it easier to add new configuration down the line. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/msm_gpu.h')
-rw-r--r--drivers/gpu/drm/msm/msm_gpu.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 636450299c33..fd8049592aae 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -28,6 +28,14 @@
struct msm_gem_submit;
struct msm_gpu_perfcntr;
+struct msm_gpu_config {
+ const char *ioname;
+ const char *irqname;
+ uint64_t va_start;
+ uint64_t va_end;
+ unsigned int ringsz;
+};
+
/* So far, with hardware that I've seen to date, we can have:
* + zero, one, or two z180 2d cores
* + a3xx or a2xx 3d core, which share a common CP (the firmware
@@ -208,7 +216,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
- const char *name, const char *ioname, const char *irqname, int ringsz);
+ const char *name, struct msm_gpu_config *config);
+
void msm_gpu_cleanup(struct msm_gpu *gpu);
struct msm_gpu *adreno_load_gpu(struct drm_device *dev);