diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2022-06-01 20:46:29 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2022-07-27 09:05:48 +1000 |
| commit | 889fcbe949bdd8470931a90b91f273ca18c510c1 (patch) | |
| tree | 8f30ff553c952128cd61ad4e3feca7a85c564066 /drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c | |
| parent | 7bcf89eed48f3fba8d0e2c19236e7dc547b6e037 (diff) | |
drm/nouveau/disp: add common channel class handling
Replaces a bunch of unnecessarily duplicated boilerplate in per-chipset
code with a simpler, common, implementation.
Channel "awaken" notify code is completely gone for now. KMS has never
made use of it so far, and event notify handling is about to be changed
in general anyway.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c index d808f6e8887c..a4853c4e5ee3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c @@ -338,13 +338,13 @@ g94_disp_core_mthd = { } }; -int -g94_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, - struct nvkm_disp *disp, struct nvkm_object **pobject) -{ - return nv50_disp_core_new_(&nv50_disp_core_func, &g94_disp_core_mthd, - disp, 0, oclass, argv, argc, pobject); -} +const struct nvkm_disp_chan_user +g94_disp_core = { + .func = &nv50_disp_core_func, + .ctrl = 0, + .user = 0, + .mthd = &g94_disp_core_mthd, +}; static const struct nvkm_disp_func g94_disp = { @@ -360,11 +360,11 @@ g94_disp = { .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, .root = { 0,0,GT206_DISP }, .user = { - {{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new }, - {{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new }, - {{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new }, - {{0,0,GT206_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new }, - {{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new }, + {{0,0, G82_DISP_CURSOR }, nvkm_disp_chan_new, & nv50_disp_curs }, + {{0,0, G82_DISP_OVERLAY }, nvkm_disp_chan_new, & nv50_disp_oimm }, + {{0,0,GT200_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base }, + {{0,0,GT206_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, & g94_disp_core }, + {{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, >200_disp_ovly }, {} }, }; |