diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-10-01 18:02:10 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-10 12:46:58 +0200 |
| commit | 939c2fe8bdb0fbf163dc8555a08c5ca863babd89 (patch) | |
| tree | d1d4ebfc692800fc56c978f20fe501093ef938dc /drivers/gpu/drm | |
| parent | 3def84b34c80518cd0375440dde8ce690795b369 (diff) | |
drm/i915: Set primary_disabled in intel_{enable, disable}_plane
If the primary gets marked as disabled while the pipe is off for
instance, we should still re-enable it when the pipe is turned on,
unless the sprite covers it fully also in that configuration.
Unfortunately we do the plane visibility checks only in the sprite code,
which is executed after the primary enabling when turning the pipe off.
Ideally we should compute the plane visibility before touching the
hardware at all, but for now just set the primary_disabld flag
in intel_{enable,disable}_plane.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a003bc572a00..579becbc46ec 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1832,12 +1832,16 @@ void intel_flush_display_plane(struct drm_i915_private *dev_priv, static void intel_enable_plane(struct drm_i915_private *dev_priv, enum plane plane, enum pipe pipe) { + struct intel_crtc *intel_crtc = + to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); int reg; u32 val; /* If the pipe isn't enabled, we can't pump pixels and may hang */ assert_pipe_enabled(dev_priv, pipe); + intel_crtc->primary_disabled = false; + reg = DSPCNTR(plane); val = I915_READ(reg); if (val & DISPLAY_PLANE_ENABLE) @@ -1859,9 +1863,13 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, static void intel_disable_plane(struct drm_i915_private *dev_priv, enum plane plane, enum pipe pipe) { + struct intel_crtc *intel_crtc = + to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); int reg; u32 val; + intel_crtc->primary_disabled = true; + reg = DSPCNTR(plane); val = I915_READ(reg); if ((val & DISPLAY_PLANE_ENABLE) == 0) |