diff options
| author | Nicolin Chen <nicoleotsuka@gmail.com> | 2020-10-07 17:37:42 -0700 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2020-10-27 09:03:56 +0100 |
| commit | c14bea053775e0c79a6fdd2d1b5a1d9de4fbd7c7 (patch) | |
| tree | 4872268640f3b9647265c406eb45b6dea7c217c3 /drivers/memory | |
| parent | 3650b228f83adda7e5ee532e2b90429c03f7b9ec (diff) | |
memory: tegra: Correct la.reg address of seswr
According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
[23:16] of register at address 0x3e0 with a reset value of 0x80
at register 0x3e0, while bit-1 of register 0xb98 is for enable
bit of seswr.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201008003746.25659-2-nicoleotsuka@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'drivers/memory')
| -rw-r--r-- | drivers/memory/tegra/tegra210.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 7fb8b5438bf4..088814279616 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .bit = 1, }, .la = { - .reg = 0xb98, + .reg = 0x3e0, .shift = 16, .mask = 0xff, .def = 0x80, |