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authorDavid Clear <dac2@pensando.io>2020-07-20 09:36:56 -0700
committerTudor Ambarus <tudor.ambarus@microchip.com>2020-07-27 08:37:06 +0300
commit1371a80cac33d5b0df4c33f918b9dd810cf4edab (patch)
tree2bcf3bcc60eff38e1d6da4ad2911fe62284ca972 /drivers/mtd/spi-nor/micron-st.c
parent48029e620decc185c88041e12156e4f5d871b28a (diff)
mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25qu02g
The Micron mt25qu02g supports both x2 and x4 transactions. Add the SPI_NOR_DUAL_READ flag to its spi_nor_ids[] table entry. Tested on Pensando SoC hardware with a cadence quadspi controller via drivers/spi/spi-cadence-quadspi.c, in x2 mode at 50MHz. - random data write, erase, read - verified erase operations - random data write, read/compare - verified write/read operations Signed-off-by: David Clear <dac2@pensando.io> Acked-by: Shannon Nelson <snelson@pensando.io> Link: https://lore.kernel.org/r/20200720163656.38006-3-dac2@pensando.io Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/mtd/spi-nor/micron-st.c')
-rw-r--r--drivers/mtd/spi-nor/micron-st.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3dca5b9af3b6..ef3695080710 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -71,8 +71,8 @@ static const struct flash_info st_parts[] = {
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
NO_CHIP_ERASE) },
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096,
- SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
- NO_CHIP_ERASE) },
+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },