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authorMaxim Mikityanskiy <maximmi@mellanox.com>2019-12-06 16:42:09 +0200
committerSaeed Mahameed <saeedm@mellanox.com>2020-05-09 01:05:40 -0700
commit2eeb6e384102e1124d0a5633803dda0cdbcac471 (patch)
treeae9a3c39f5f9ca57607d2bd151df72c4ed2ad4ff /drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
parent0bdb078c74854c48bffa323899f2e0c5ca924e72 (diff)
net/mlx5e: Make TLS offload independent of wqe and pi
TLS offload may write a 32-bit field (tisn) to the cseg of the WQE. To do that, it receives pi and wqe pointers. As TLS offload may also send additional WQEs, it has to update pi and wqe, and in many cases it even doesn't use pi calculated before and wqe zeroed before and does it itself. Also, mlx5e_sq_xmit has to copy the whole cseg if it goes to the mlx5e_fill_sq_frag_edge flow. This all is not efficient. It's more efficient to do the following: 1. Just return tisn from TLS offload and make the caller fill it in a more appropriate place. 2. Calculate pi and clear wqe after calling TLS offload. 3. If TLS offload has to send WQEs, calculate pi and clear wqe just before that. It's already done in all places anyway, so this commit allows to remove some redundant memsets and calls. Copying of cseg will be eliminated in one of the following commits, and all other stuff is done here. Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h')
-rw-r--r--drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
index c658c8556863..66bfab021d6b 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
@@ -109,10 +109,18 @@ static inline bool mlx5e_accel_handle_tx(struct sk_buff *skb,
u16 *pi)
{
#ifdef CONFIG_MLX5_EN_TLS
+ u32 tls_tisn = 0;
+
if (test_bit(MLX5E_SQ_STATE_TLS, &sq->state)) {
- if (unlikely(!mlx5e_tls_handle_tx_skb(dev, sq, skb, wqe, pi)))
+ /* May send SKBs and WQEs. */
+ if (unlikely(!mlx5e_tls_handle_tx_skb(dev, sq, skb, &tls_tisn)))
return false;
}
+
+ *pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
+ *wqe = MLX5E_TX_FETCH_WQE(sq, *pi);
+
+ (*wqe)->ctrl.tisn = cpu_to_be32(tls_tisn << 8);
#endif
#ifdef CONFIG_MLX5_EN_IPSEC