diff options
| author | Jaehoon Chung <jh80.chung@samsung.com> | 2015-04-08 21:03:57 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:44:35 +0900 |
| commit | 731cae2020c6dbb2f233196d72be10ef0128f926 (patch) | |
| tree | f59bd41a1e96a8247c9b55ac56e9cde717f53862 /drivers/pci | |
| parent | d5c6befb91462b338d863fdd381dca58ea05a5a4 (diff) | |
local/pci: pcie-designware: enable DBI_RO_WR_EN bit
If DBI_RO_WR_EN bit is enabled, some RO and HWinit bits are writable
from the local application through the DBI.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index e7916c3031d4..7c775c95e667 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -46,6 +46,9 @@ #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define DBI_RO_WR_EN 0x1 + #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) @@ -68,7 +71,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C - static unsigned long global_io_offset; static struct pci_ops dw_pcie_ops; @@ -811,6 +813,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 membase; u32 memlimit; + /* + * Enable DBI_RO_WR_EN bit. + * - When set to 1, some RO and Hwinit bits are writable + * from the local application through the DBI. + */ + dw_pcie_writel_rc(pp, DBI_RO_WR_EN, PCIE_MISC_CONTROL_1_OFF); + /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); val &= ~PORT_LINK_MODE_MASK; |