diff options
| author | Shah, Nehal-bakulchandra <Nehal-Bakulchandra.shah@amd.com> | 2016-12-06 12:17:48 +0530 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-12-28 13:26:09 +0100 |
| commit | 3bfd44306c65d073008b9ca8f062249f35576b61 (patch) | |
| tree | 386837ae222e1889feac176ce768334ceb72dd8b /drivers/pinctrl/pinctrl-amd.h | |
| parent | b75dd8722e1779767a018009ab6550de33a9136e (diff) | |
pinctrl: amd: Add support for additional GPIO
This patch adds support for new Bank and adds IRQCHIP_SKIP_SET_WAKE flag.
Reviewed-by: S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com>
Signed-off-by: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-amd.h')
| -rw-r--r-- | drivers/pinctrl/pinctrl-amd.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 7bfea47dbb47..c03f77822069 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -13,13 +13,12 @@ #ifndef _PINCTRL_AMD_H #define _PINCTRL_AMD_H -#define TOTAL_NUMBER_OF_PINS 192 #define AMD_GPIO_PINS_PER_BANK 64 -#define AMD_GPIO_TOTAL_BANKS 3 #define AMD_GPIO_PINS_BANK0 63 #define AMD_GPIO_PINS_BANK1 64 #define AMD_GPIO_PINS_BANK2 56 +#define AMD_GPIO_PINS_BANK3 32 #define WAKE_INT_MASTER_REG 0xfc #define EOI_MASK (1 << 29) @@ -35,7 +34,9 @@ #define ACTIVE_LEVEL_OFF 9 #define INTERRUPT_ENABLE_OFF 11 #define INTERRUPT_MASK_OFF 12 -#define WAKE_CNTRL_OFF 13 +#define WAKE_CNTRL_OFF_S0I3 13 +#define WAKE_CNTRL_OFF_S3 14 +#define WAKE_CNTRL_OFF_S4 15 #define PIN_STS_OFF 16 #define DRV_STRENGTH_SEL_OFF 17 #define PULL_UP_SEL_OFF 19 @@ -93,6 +94,7 @@ struct amd_gpio { u32 ngroups; struct pinctrl_dev *pctrl; struct gpio_chip gc; + unsigned int hwbank_num; struct resource *res; struct platform_device *pdev; }; |