Merge tag 'pinctrl-v3.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control changes from Linus Walleij:
 "Here is the bulk of pin control changes for the v3.12 series.  Most of
  the relevant information is in the tag.

  I merged in v3.11-rc7 last week to get rid of a largeish conflict
  within the sunxi (AllWinner) driver in linux-next and fix up the
  non-trivial merge the right way.  That driver had a rather large fix
  adding locking late in the release cycle.

  Overall the bulk changes this time is cleanups and refactorings and
  not much new features, which is nice.

   - Refactorings for generic pin config handling in the core.

   - Factor out a set of device tree utilities for use in all drivers,
     to parse and allocate maps from the device tree.

   - Some fixes to the core such as more nitpicky locking.

   - Pushed down config array iteration into the drivers.

     This patch is necessary for drivers that want to iterate over
     configs and pile up a stack of alterations to the same register(s),
     or if the driver wants to take a local spinlock when committing the
     configuration.

   - A new driver for the Texas Instruments Palmas PMIC by Laxman
     Dewangan.  This is used on the Tegra systems.

   - A major cleanup and modernization of the PFC (Super Hitachi and ARM
     SHmobile) pin controller and subdrivers.

   - Support for the A20 and A31 sunxi (AllWinner) SoCs.

   - A huge pile of fixes and cleanups: Axel Lin, Jingoo Han Dan
     Carpenter, Julia Lawall and Sachin Kamat did an excellent job here"

* tag 'pinctrl-v3.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (124 commits)
  pinctrl: sunxi: Fix off-by-one for valid offset range checking
  pinctrl: sunxi: drop lock on error path
  pinctrl: pinconf-generic: Remove ti prefix in dev_err messages
  pinctrl: rockchip: Implement .request() and .free() callbacks
  pinctrl: at91: fix get_pullup/down function return
  pinctrl: sh-pfc: remove unnecessary platform_set_drvdata()
  pinctrl: Add s5pv210 support to pinctrl-exynos
  pinctrl: utils: include export.h to avoid warnings
  pinctrl: s3c24xx: off by one in s3c24xx_eint_init()
  pinctrl: mvebu: testing the wrong variable
  pinctrl: abx500: fix bitwise AND test
  pinctrl: mvebu: Convert to use devm_ioremap_resource
  pinctrl: Pass all configs to driver on pin_config_set()
  pinctrl: tz1090-pdc: Convert to devm_ioremap_resource
  pinctrl: tz1090: Convert to devm_ioremap_resource
  pinctrl: tegra: Convert to devm_ioremap_resource
  pinctrl: rockchip: Simplify pin_to_bank equation
  pinctrl: spear: Convert to devm_ioremap_resource
  pinctrl: rockchip: Remove of_match_ptr macro for DT only driver
  pinctrl: palmas: PINCTRL_PALMAS needs to select PINMUX
  ...

1 files changed, 61 insertions, 52 deletions

diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
index 3b283fd898ff..544d469c5a7b 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -401,64 +401,71 @@ static const struct pinmux_ops exynos5440_pinmux_ops = {
 
 /* set the pin config settings for a specified pin */
 static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
-				unsigned long config)
+				unsigned long *configs,
+				unsigned num_configs)
 {
 	struct exynos5440_pinctrl_priv_data *priv;
 	void __iomem *base;
-	enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
-	u32 cfg_value = PINCFG_UNPACK_VALUE(config);
+	enum pincfg_type cfg_type;
+	u32 cfg_value;
 	u32 data;
+	int i;
 
 	priv = pinctrl_dev_get_drvdata(pctldev);
 	base = priv->reg_base;
 
-	switch (cfg_type) {
-	case PINCFG_TYPE_PUD:
-		/* first set pull enable/disable bit */
-		data = readl(base + GPIO_PE);
-		data &= ~(1 << pin);
-		if (cfg_value)
-			data |= (1 << pin);
-		writel(data, base + GPIO_PE);
-
-		/* then set pull up/down bit */
-		data = readl(base + GPIO_PS);
-		data &= ~(1 << pin);
-		if (cfg_value == 2)
-			data |= (1 << pin);
-		writel(data, base + GPIO_PS);
-		break;
-
-	case PINCFG_TYPE_DRV:
-		/* set the first bit of the drive strength */
-		data = readl(base + GPIO_DS0);
-		data &= ~(1 << pin);
-		data |= ((cfg_value & 1) << pin);
-		writel(data, base + GPIO_DS0);
-		cfg_value >>= 1;
-
-		/* set the second bit of the driver strength */
-		data = readl(base + GPIO_DS1);
-		data &= ~(1 << pin);
-		data |= ((cfg_value & 1) << pin);
-		writel(data, base + GPIO_DS1);
-		break;
-	case PINCFG_TYPE_SKEW_RATE:
-		data = readl(base + GPIO_SR);
-		data &= ~(1 << pin);
-		data |= ((cfg_value & 1) << pin);
-		writel(data, base + GPIO_SR);
-		break;
-	case PINCFG_TYPE_INPUT_TYPE:
-		data = readl(base + GPIO_TYPE);
-		data &= ~(1 << pin);
-		data |= ((cfg_value & 1) << pin);
-		writel(data, base + GPIO_TYPE);
-		break;
-	default:
-		WARN_ON(1);
-		return -EINVAL;
-	}
+	for (i = 0; i < num_configs; i++) {
+		cfg_type = PINCFG_UNPACK_TYPE(configs[i]);
+		cfg_value = PINCFG_UNPACK_VALUE(configs[i]);
+
+		switch (cfg_type) {
+		case PINCFG_TYPE_PUD:
+			/* first set pull enable/disable bit */
+			data = readl(base + GPIO_PE);
+			data &= ~(1 << pin);
+			if (cfg_value)
+				data |= (1 << pin);
+			writel(data, base + GPIO_PE);
+
+			/* then set pull up/down bit */
+			data = readl(base + GPIO_PS);
+			data &= ~(1 << pin);
+			if (cfg_value == 2)
+				data |= (1 << pin);
+			writel(data, base + GPIO_PS);
+			break;
+
+		case PINCFG_TYPE_DRV:
+			/* set the first bit of the drive strength */
+			data = readl(base + GPIO_DS0);
+			data &= ~(1 << pin);
+			data |= ((cfg_value & 1) << pin);
+			writel(data, base + GPIO_DS0);
+			cfg_value >>= 1;
+
+			/* set the second bit of the driver strength */
+			data = readl(base + GPIO_DS1);
+			data &= ~(1 << pin);
+			data |= ((cfg_value & 1) << pin);
+			writel(data, base + GPIO_DS1);
+			break;
+		case PINCFG_TYPE_SKEW_RATE:
+			data = readl(base + GPIO_SR);
+			data &= ~(1 << pin);
+			data |= ((cfg_value & 1) << pin);
+			writel(data, base + GPIO_SR);
+			break;
+		case PINCFG_TYPE_INPUT_TYPE:
+			data = readl(base + GPIO_TYPE);
+			data &= ~(1 << pin);
+			data |= ((cfg_value & 1) << pin);
+			writel(data, base + GPIO_TYPE);
+			break;
+		default:
+			WARN_ON(1);
+			return -EINVAL;
+		}
+	} /* for each config */
 
 	return 0;
 }
@@ -510,7 +517,8 @@ static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 
 /* set the pin config settings for a specified pin group */
 static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
-			unsigned group, unsigned long config)
+			unsigned group, unsigned long *configs,
+			unsigned num_configs)
 {
 	struct exynos5440_pinctrl_priv_data *priv;
 	const unsigned int *pins;
@@ -520,7 +528,8 @@ static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
 	pins = priv->pin_groups[group].pins;
 
 	for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
-		exynos5440_pinconf_set(pctldev, pins[cnt], config);
+		exynos5440_pinconf_set(pctldev, pins[cnt], configs,
+				       num_configs);
 
 	return 0;
 }