diff options
| author | Gil Fine <gil.fine@intel.com> | 2021-12-17 03:16:43 +0200 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2021-12-28 10:43:56 +0300 |
| commit | 43f977bc60b1cfd3c1d220a9a0a06493fbf3985d (patch) | |
| tree | e1dd6423c1c4b1e0defc5454a90f09f041a2b105 /drivers/thunderbolt/tb.c | |
| parent | 483c9d8275aff428df433e9d7c718609345500e2 (diff) | |
thunderbolt: Enable CL0s for Intel Titan Ridge
Low power link states (called collectively CLx) are used to reduce
transmitter and receiver power when a high-speed lane is idle. The
simplest one being called CL0s. Follow what we already do for USB4
device routers and enable CL0s for Intel Titan Ridge device router too.
This allows better thermal management.
Signed-off-by: Gil Fine <gil.fine@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt/tb.c')
| -rw-r--r-- | drivers/thunderbolt/tb.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c index 1454dc5b6b91..cbd0ad85ffb1 100644 --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c @@ -1092,6 +1092,13 @@ static int tb_tunnel_pci(struct tb *tb, struct tb_switch *sw) return -EIO; } + /* + * PCIe L1 is needed to enable CL0s for Titan Ridge so enable it + * here. + */ + if (tb_switch_pcie_l1_enable(sw)) + tb_sw_warn(sw, "failed to enable PCIe L1 for Titan Ridge\n"); + list_add_tail(&tunnel->list, &tcm->tunnel_list); return 0; } |