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authorMatt Roper <matthew.d.roper@intel.com>2021-07-23 10:42:32 -0700
committerMatt Roper <matthew.d.roper@intel.com>2021-07-29 09:05:25 -0700
commit29081008047892acb39099c39d39f84c2e7fb028 (patch)
treeaade3202ded97a9cdb41443ff8dbd3a0b5ee8e12 /fs
parent65ad82b2a3e89bbad6a9337b91dab36798e198dd (diff)
drm/i915/dg2: Add MPLLB programming for SNPS PHY
DG2's SNPS PHYs incorporate a dedicated port PLL called MPLLB which takes the place of the shared DPLLs we've used on past platforms. Let's add the MPLLB programming sequences; they'll be plugged into the rest of the code in future patches. Bspec: 54032 Bspec: 53881 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Nidhi Gupta <nidhi1.gupta@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-24-matthew.d.roper@intel.com
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