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| author | Dan Williams <dan.j.williams@intel.com> | 2023-02-14 15:06:08 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-02-14 15:06:08 -0800 |
| commit | 5a6fe61facdb7f830895712b31fb39f544ffc165 (patch) | |
| tree | 5a276223390d2304152b5512bef5bfd2b5ba4ecf /include/uapi | |
| parent | ee817acaa01d5c56e5fef396bea05c869b7e9351 (diff) | |
| parent | 248529edc86f8d7d390a15a86bd1904951311665 (diff) | |
Merge branch 'for-6.3/cxl' into cxl/next
Pick up the AER unmasking patches for v6.3.
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 85ab1278811e..dc2000e0fe3a 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -693,6 +693,7 @@ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */ +#define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */ #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */ #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */ |