diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2015-09-01 11:22:18 +0200 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:50:34 +0900 |
| commit | 77d83016100c1433255e6351b54d0ba7cf241dea (patch) | |
| tree | 7b8cc41980b394165e59259b7adb9a5d7473bd02 /include | |
| parent | 5d36736404a5802d9478ca3e38808e86af6875a2 (diff) | |
clk: samsung: exynos5422: add missing parent GSCL block clocks
This patch adds clocks, which are required for preserving parent clock
configuration on GSCALLER power domain on/off.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/exynos5420.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index dde96643e585..7699ee9c16c0 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -212,6 +212,8 @@ #define CLK_MOUT_SW_ACLK300 649 #define CLK_MOUT_USER_ACLK400_DISP1 650 #define CLK_MOUT_SW_ACLK400 651 +#define CLK_MOUT_USER_ACLK300_GSCL 652 +#define CLK_MOUT_SW_ACLK300_GSCL 653 /* divider clocks */ #define CLK_DOUT_PIXEL 768 |