diff options
| author | Chanwoo Choi <cw00.choi@samsung.com> | 2015-07-17 20:48:38 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:50:25 +0900 |
| commit | b5da7d38c69a55168d59f9c2ea287f4672f5dcd2 (patch) | |
| tree | 84a84bbb099cf237f9fb32822fdc8cdc92837832 /include | |
| parent | 9cb787642ad40746437637245fc0a5122b5f904a (diff) | |
clk: samsung: exynos3250: Add MMC2 clock
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
Change-Id: Ib0c194e09f6ed171ba1a84a35a96f651b615666f
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/exynos3250.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 89a7d97b002c..fbc9ef61b191 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,7 @@ #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 #define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -128,6 +129,8 @@ #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 #define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -225,6 +228,7 @@ #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 #define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -252,12 +256,13 @@ #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 #define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 249 +#define CLK_NR_CLKS 250 /* * CMU DMC |