diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2021-09-01 15:26:42 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-09-01 15:26:45 -0700 |
| commit | 1faa7cb2b066a3f8966a1311d574832ccb93a72c (patch) | |
| tree | 47e3299c00c2407417fdb957d182ad9f10832f32 /include | |
| parent | 7110569a096d820876f99543660741bd8a96af7c (diff) | |
| parent | e81b917a78c7ed08007de5b502a14535daa106bf (diff) | |
Merge branch 'clk-frac-divider' into clk-next
- Add power of two flag to fractional divider clk type
* clk-frac-divider:
clk: fractional-divider: Document the arithmetics used behind the code
clk: fractional-divider: Introduce POWER_OF_TWO_PS flag
clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience
clk: fractional-divider: Export approximation algorithm to the CCF users
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/clk-provider.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 7be81d5fcf8c..f59c875271a0 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1001,6 +1001,12 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are * used for the divider register. Setting this flag makes the register * accesses big endian. + * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might + * be saturated and the caller will get quite far from the good enough + * approximation. Instead the caller may require, by setting this flag, + * to shift left by a few bits in case, when the asked one is quite small + * to satisfy the desired range of denominator. It assumes that on the + * caller's side the power-of-two capable prescaler exists. */ struct clk_fractional_divider { struct clk_hw hw; @@ -1020,10 +1026,10 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) -#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) -#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) +#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) +#define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2) -extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, |