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authorAntonio Borneo <antonio.borneo@foss.st.com>2021-12-18 22:50:54 +0100
committerRobert Foss <robert.foss@linaro.org>2022-01-04 12:54:02 +0100
commite01356d18273bd52bc88179f907b9d12978ebddd (patch)
tree4760c7b2ce5ec007f32f647cd92af125641d5993 /net/ipv4/tunnel4.c
parent5f4f958a0d9dfd7a569c56e76840e39b0c434378 (diff)
drm/stm: dsi: provide the implementation of mode_valid()
The dsi has several constraints on the video modes it can support, mainly due to the frequencies that can be generated by the PLL integrated in the DSI device. Verify that the required HS clock can be generated by the PLL. The dsi clock from the dsi PLL and the ltdc pixel clock are asynchronous. The dsi needs to return in LP mode during HFP or HBP to re-synchronize at each video line. Verify that the duration of HFP and HBP allows the dsi to enter in LP mode. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Acked-by: Philippe Cornu <philippe.cornu@foss.st.com> Reviewed-by: Philippe Cornu <philippe.cornu@foss.st.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20211218215055.212421-3-antonio.borneo@foss.st.com
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