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| author | Pratyush Yadav <p.yadav@ti.com> | 2020-12-23 00:14:22 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-01-06 13:08:44 +0000 |
| commit | 7512eaf54190e4cc9247f18439c008d44b15022c (patch) | |
| tree | 7dba024aa1489352f5b5c9ec1623ac7e9b8216b0 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 888d517b992532df2b6115fbdc9620673ca7c651 (diff) | |
spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1
SPI MEM deals with dummy bytes but the controller deals with dummy
cycles. Multiplying bytes by 8 is correct if the dummy phase uses 1S
mode since 1 byte will be sent in 8 cycles. But if the dummy phase uses
4S mode then 1 byte will be sent in 2 cycles.
To correctly translate dummy bytes to dummy cycles, the dummy buswidth
also needs to be taken into account. Divide 8 by the buswidth to get the
correct multiplier for getting the number of cycles.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-5-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions