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authorYong Wu <yong.wu@mediatek.com>2021-09-14 19:37:02 +0800
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-09-22 08:43:09 +0200
commitfe6dd2a4017d3dfbf4a530d95270a1d498a16a4c (patch)
tree56f7962d68c5a5e3472d37c39c4ce93eb9e9abd6 /tools/perf/scripts/python/export-to-postgresql.py
parent431e9cab7097b5d5eb3cf2b04d4b12d272df85e0 (diff)
memory: mtk-smi: mt8195: Add initial setting for smi-larb
To improve the performance, We add some initial setting for smi larbs. there are two part: 1), Each port has the special ostd(outstanding) value in each larb. 2), Two general settings for each larb. a. THRT_UPDATE: the value in bits[7:4] of 0x24 is not so good. The HW default is 4, and we expect it is 5, thus, add a flag to update it. This is only a DE recommendatory value, not a actual issue. The register name(THRT_CON) means: throttling control, and the field RD_NU_LMT means: Read Non-ultra commands limit. This change means update the Read non-ultra command from 4 to 5 here. b. SW_FLAG: Set 1 to the FLAG register. this is only for helping debug. We could confirm if the larb is reset from this value is 1 or 0. In some SoC, this setting maybe changed dynamically for some special case like 4K, and this initial setting is enough in mt8195. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Link: https://lore.kernel.org/r/20210914113703.31466-13-yong.wu@mediatek.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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