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authorjames qian wang (Arm Technology China) <james.qian.wang@arm.com>2019-06-05 11:35:32 +0100
committerLiviu Dudau <Liviu.Dudau@arm.com>2019-06-19 11:42:17 +0100
commit28be315c9c0c0b8d1093fcddf3245398108b83fd (patch)
treeaf1a3825781902e624f7f6947b251f5806d2103b /tools/perf/scripts/python/export-to-sqlite.py
parent109bd7d5f4c2db66541272e5a41aeabd6cfeef95 (diff)
drm/komeda: Unify mclk/pclk/pipeline->aclk to one MCLK
Current komeda driver uses three dedicated clks for a specific purpose: - mclk: main engine clock - pclk: APB clock - pipeline->aclk: AXI clock. But per spec the komeda HW only has three input clks: - ACLK: used for AXI masters, APB slave and most pipeline processing - PXCLK for pipeline 0: output pixel clock for pipeline 0 - PXCLK for pipeline 1: output pixel clock for pipeline 1 So one ACLK is enough, no need to split it to three mclk/pclk/axiclk. drop pclk/pipeline->axiclk. but only keep one mclk in komeda driver. Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
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