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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-04-23 22:40:47 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-04-28 09:54:25 +0200 |
| commit | 41b2df22fafbca2c69dcce9f93c7042e6ccd69ef (patch) | |
| tree | 4b0a1c64bbfe9a2b260669df5c7bce943be0cf40 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 58f7381c97547db025970423bd2a3b9d9cea1174 (diff) | |
clk: renesas: Add r8a7742 CPG Core Clock Definitions
Add all RZ/G1H Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [RZ/G1H]") of the RZ/G1 Hardware User's
Manual.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions