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| author | Qi Liu <liuqi115@huawei.com> | 2020-09-16 18:48:51 +0800 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2020-09-16 10:54:02 -0300 |
| commit | ce9c13f31b10560d4e4d801f9f94895f595756aa (patch) | |
| tree | 5358ba00a8863eca057c7485fbdf936971eda3be /tools/perf/scripts/python/intel-pt-events.py | |
| parent | d26383dcb2b4b8629fde05270b4e3633be9e3d4b (diff) | |
perf stat: Fix the ratio comments of miss-events
'perf stat' displays miss ratio of L1-dcache, L1-icache, dTLB cache,
iTLB cache and LL-cache. Take L1-dcache for example, miss ratio is
caculated as "L1-dcache-load-misses/L1-dcache-loads". So "of all
L1-dcache hits" is unsuitable to describe it, and "of all L1-dcache
accesses" seems better.
The comments of L1-icache, dTLB cache, iTLB cache and LL-cache are
fixed in the same way.
Signed-off-by: Qi Liu <liuqi115@huawei.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1600253331-10535-1-git-send-email-liuqi115@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/intel-pt-events.py')
0 files changed, 0 insertions, 0 deletions