diff options
| author | Sanket Goswami <Sanket.Goswami@amd.com> | 2022-02-04 17:55:27 +0530 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2022-02-17 14:07:25 +0100 |
| commit | 3d7d407dfb05b257e15cb0c6b056428a4a8c2e5d (patch) | |
| tree | 8a5dc8516898e50d91264fca486b8a5ddc77df77 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | dbce412a7733bb7a763d99db413da22da72e3736 (diff) | |
platform/x86: amd-pmc: Add support for AMD Spill to DRAM STB feature
Spill to DRAM functionality is a feature that allows STB (Smart Trace
Buffer) to spill data from SRAM into DRAM on some future AMD ASICs. The
size allocated for STB is more than the earlier SoC's which helps to
collect more tracing and telemetry data.
Co-developed-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20220204122527.3873552-1-Sanket.Goswami@amd.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions