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author | Yong Wu <yong.wu@mediatek.com> | 2021-09-14 19:36:52 +0800 |
---|---|---|
committer | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-09-22 08:40:10 +0200 |
commit | 599e681a31a2dfa7359b8e420a1157ed015f840b (patch) | |
tree | 32c35f596ce8778a1c5e685585e0c44315985821 /tools/perf/scripts/python/stackcollapse.py | |
parent | b01065eee432b3ae91a2c0aaab66c2cae2e9812d (diff) |
dt-bindings: memory: mediatek: Add mt8195 smi sub common
Add the binding for smi-sub-common. The SMI block diagram like this:
IOMMU
| |
smi-common
------------------
| .... |
larb0 larb7 <-max is 8
The smi-common connects with smi-larb and IOMMU. The maximum larbs number
that connects with a smi-common is 8. If the engines number is over 8,
sometimes we use a smi-sub-common which is nearly same with smi-common.
It supports up to 8 input and 1 output(smi-common has 2 output)
Something like:
IOMMU
| |
smi-common
---------------------
| | ...
larb0 sub-common ... <-max is 8
-----------
| | ... <-max is 8 too.
larb2 larb5
We don't need extra SW setting for smi-sub-common, only the sub-common has
special clocks need to enable when the engines access dram.
If it is sub-common, it should have a "mediatek,smi" phandle to point to
its smi-common. meanwhile the sub-common only has one gals clock.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210914113703.31466-3-yong.wu@mediatek.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions